am29lv160d.vhd

在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d）

        w_20 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15);
        w_21 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14);
        w_22 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13);
        w_23 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12);
        w_24 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11);
        w_25 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10);
        w_26 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9);
        w_27 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8);
        w_28 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7);
        w_29 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6);
        w_30 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5);
        w_31 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4);
        w_32 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3);
        w_33 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2);
        w_34 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1);
        w_35 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0);
        w_36 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
        w_37 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
        w_38 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg);
        w_39 : VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg);
        w_40 : VitalWireDelay (BYTENeg_ipd, BYTENeg, tipd_BYTENeg);

    END BLOCK;

    ---------------------------------------------------------------------------
    -- Main Behavior Block
    ---------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            A              : IN    std_logic_vector(HiAddrBit downto 0) :=
                                               (OTHERS => 'U');
            DIn            : IN    std_logic_vector(15 downto 0) :=
                                               (OTHERS => 'U');
            DOut           : OUT   std_ulogic_vector(15 downto 0) :=
                                               (OTHERS => 'Z');
            CENeg          : IN    std_ulogic := 'U';
            OENeg          : IN    std_ulogic := 'U';
            WENeg          : IN    std_ulogic := 'U';
            RESETNeg       : IN    std_ulogic := 'U';
            BYTENeg        : IN    std_ulogic := 'U';
            RY             : OUT   std_ulogic := 'U'
        );
        PORT MAP (
            A(19)    => A19_ipd,
            A(18)    => A18_ipd,
            A(17)    => A17_ipd,
            A(16)    => A16_ipd,
            A(15)    => A15_ipd,
            A(14)    => A14_ipd,
            A(13)    => A13_ipd,
            A(12)    => A12_ipd,
            A(11)    => A11_ipd,
            A(10)    => A10_ipd,
            A(9)     => A9_ipd,
            A(8)     => A8_ipd,
            A(7)     => A7_ipd,
            A(6)     => A6_ipd,
            A(5)     => A5_ipd,
            A(4)     => A4_ipd,
            A(3)     => A3_ipd,
            A(2)     => A2_ipd,
            A(1)     => A1_ipd,
            A(0)     => A0_ipd,

            DIn(15)  => DQ15_ipd,
            DIn(14)  => DQ14_ipd,
            DIn(13)  => DQ13_ipd,
            DIn(12)  => DQ12_ipd,
            DIn(11)  => DQ11_ipd,
            DIn(10)  => DQ10_ipd,
            DIn(9)   => DQ9_ipd,
            DIn(8)   => DQ8_ipd,
            DIn(7)   => DQ7_ipd,
            DIn(6)   => DQ6_ipd,
            DIn(5)   => DQ5_ipd,
            DIn(4)   => DQ4_ipd,
            DIn(3)   => DQ3_ipd,
            DIn(2)   => DQ2_ipd,
            DIn(1)   => DQ1_ipd,
            DIn(0)   => DQ0_ipd,

            DOut(15) => DQ15,
            DOut(14) => DQ14,
            DOut(13) => DQ13,
            DOut(12) => DQ12,
            DOut(11) => DQ11,
            DOut(10) => DQ10,
            DOut(9)  => DQ9,
            DOut(8)  => DQ8,
            DOut(7)  => DQ7,
            DOut(6)  => DQ6,
            DOut(5)  => DQ5,
            DOut(4)  => DQ4,
            DOut(3)  => DQ3,
            DOut(2)  => DQ2,
            DOut(1)  => DQ1,
            DOut(0)  => DQ0,

            CENeg    => CENeg_ipd,
            OENeg    => OENeg_ipd,
            WENeg    => WENeg_ipd,
            RESETNeg => RESETNeg_ipd,
            BYTENeg  => BYTENeg_ipd,
            RY       => RY
        );

        -- State Machine : State_Type
        TYPE state_type IS (
                            RESET,
                            Z001,
                            PREL_SETBWB,
                            PREL_ULBYPASS,
                            CFI_U,
                            CFI,
                            AS,
                            A0SEEN,
                            C8,
                            C8_Z001,
                            C8_PREL,
                            ERS,
                            SERS,
                            ESPS,
                            SERS_EXEC,
                            ESP,
                            ESP_Z001,
                            ESP_PREL,
                            ESP_CFI_U,
                            ESP_CFI,
                            ESP_A0SEEN,
                            ESP_AS,
                            PGMS
                            );

        --Array of Sub sector start-end address within sector
        TYPE SubSecSEAddr IS ARRAY (0 TO SubSecNum) OF
                     NATURAL;

        --Addresses of all Sectors devided to sub sectors
        TYPE SubSecAddr IS ARRAY (0 TO 1) OF
                     SubSecSEAddr;--SecType;
        
        --Flash Memory Array
        TYPE SecType  IS ARRAY (0 TO SecSize) OF
                         INTEGER RANGE -1 TO MaxData;

        TYPE MemArray IS ARRAY (0 TO SecNum) OF
                         SecType;

        -- states
        SIGNAL current_state    : state_type;  --
        SIGNAL next_state       : state_type;  --

        -- powerup
        SIGNAL PoweredUp        : std_logic := '0';

        --zero delay signals
        SIGNAL DOut_zd          : std_logic_vector(15 downto 0):=(OTHERS=>'Z');
        SIGNAL RY_zd            : std_logic := 'Z';

        --FSM control signals
        SIGNAL ULBYPASS         : std_logic := '0'; --Unlock Bypass Active
        SIGNAL ESP_ACT          : std_logic := '0'; --Erase Suspend

        --Model should never hang!!!!!!!!!!!!!!!
        SIGNAL HANG             : std_logic := '0';

        SIGNAL PDONE            : std_logic := '1'; --Prog. Done
        SIGNAL PSTART           : std_logic := '0'; --Start Programming
        
        --Program location is in protected sector
        SIGNAL PERR             : std_logic := '0';

        SIGNAL EDONE            : std_logic := '1'; --Ers. Done
        SIGNAL ESTART           : std_logic := '0'; --Start Erase
        SIGNAL ESUSP            : std_logic := '0'; --Suspend Erase
        SIGNAL ERES             : std_logic := '0'; --Resume Erase
        --All sectors selected for erasure are protected
        SIGNAL EERR             : std_logic := '0';
        --Sectors selected for erasure
        SIGNAL ERS_QUEUE        : std_logic_vector(SecNum downto 0) :=
                                                   (OTHERS => '0');
        SIGNAL ERS_SUB_QUEUE    : std_logic_vector(SubSecNum downto 0) :=
                                                   (OTHERS => '0');

        --Command Register
        SIGNAL write            : std_logic := '0';
        SIGNAL read             : std_logic := '0';

        --Sector Address
        SIGNAL SecAddr          : NATURAL RANGE 0 TO SecNum := 0;
        SIGNAL SubSect          : NATURAL RANGE 0 TO SubSecNum := 0;

        SIGNAL SA               : NATURAL RANGE 0 TO SecNum := 0;
        SIGNAL SSA              : NATURAL RANGE 0 TO SubSecNum := 0;

        --Address within sector
        SIGNAL Address          : NATURAL RANGE 0 TO SecSize := 0;

        SIGNAL D_tmp0 : NATURAL RANGE 0 TO MaxData;
        SIGNAL D_tmp1 : NATURAL RANGE 0 TO MaxData;

        --A19:A11 Don't Care
        SIGNAL Addr             : NATURAL RANGE 0 TO 16#7FF# := 0;

        --glitch protection
        SIGNAL gWE_n            : std_logic;-- := '1';
        SIGNAL gCE_n            : std_logic;-- := '1';
        SIGNAL gOE_n            : std_logic;-- := '1';

        SIGNAL RST              : std_logic := '1';
        SIGNAL reseted          : std_logic := '0';

            -- Mem(SecAddr)(Address)....
        SHARED VARIABLE Mem         : MemArray := (OTHERS =>(OTHERS=> MaxData));

        SHARED VARIABLE Sec_Prot    : std_logic_vector(SecNum downto 0) :=
                                                   (OTHERS => '0');
        SHARED VARIABLE SubSec_Prot : std_logic_vector(SubSecNum downto 0) :=
                                                   (OTHERS => '0');
        --am29lv160dt
        SHARED VARIABLE sssa        : SubSecAddr :=
                                   ((16#0000#, 16#4000#, 16#6000#, 16#8000#),
                                    ( 16#0000#, 16#8000#, 16#A000#, 16#C000#));

        SHARED VARIABLE ssea        : SubSecAddr:=
                                   ((16#3FFF#, 16#5FFF#, 16#7FFF#, 16#FFFF#),
                                    (16#7FFF#, 16#9FFF#, 16#BFFF#, 16#FFFF#));

        -- timing check violation
        SIGNAL Viol                : X01 := '0';

        --Address of variable size sector (bottom or top boot sector)
        SIGNAL VarSect             : INTEGER := -1;
        SIGNAL vs                  : INTEGER;--0 if VarSect = 0 else 1

    PROCEDURE RestoreSectAddr (
                       VARIABLE A           : IN NATURAL RANGE 0 TO MemSize;
                       VARIABLE SecAddr     : INOUT NATURAL RANGE 0 TO SecNum;
                       VARIABLE A_tmp       : INOUT NATURAL RANGE 0 TO SecSize
                       ) IS
        VARIABLE SA_tmp      : NATURAL RANGE 0 TO SecNum;
    BEGIN

        FOR i IN 0 TO SecNum LOOP
            IF A >= i*(SecSize+1) AND A <= i*(SecSize+1) + SecSize THEN
                SecAddr := i;
                A_tmp := A - i*(SecSize + 1);
            END IF;
        END LOOP;

    END RestoreSectAddr;


    BEGIN

    ---------------------------------------------------------------------------
    --VarSect
    ---------------------------------------------------------------------------
    VarSect <= SecNum WHEN TimingModel(1 to 11)="am29lv160dt" ELSE
             0;--WHEN TimingModel = "AM29LV160DB"

    vs <= 1 WHEN TimingModel(1 to 11)="am29lv160dt" ELSE
              0;

   ----------------------------------------------------------------------------
    --Power Up time 100 ns;
    ---------------------------------------------------------------------------
    PoweredUp <= '1' AFTER 100 ns;

    RST <= RESETNeg AFTER 500 ns;

    ---------------------------------------------------------------------------
    -- VITAL Timing Checks Procedures
    ---------------------------------------------------------------------------
    VITALTimingCheck: PROCESS(A, Din, CENeg, OENeg, WENeg, RESETNeg)
         -- Timing Check Variables
        VARIABLE Tviol_A0_CENeg        : X01 := '0';
        VARIABLE TD_A0_CENeg           : VitalTimingDataType;

        VARIABLE Tviol_A0_WENeg        : X01 := '0';
        VARIABLE TD_A0_WENeg           : VitalTimingDataType;

        VARIABLE Tviol_BYTENeg_WENeg   : X01 := '0';
        VARIABLE TD_BYTENeg_WENeg      : VitalTimingDataType;

        VARIABLE Tviol_DQ0_CENeg       : X01 := '0';
        VARIABLE TD_DQ0_CENeg          : VitalTimingDataType;

        VARIABLE Tviol_DQ0_WENeg       : X01 := '0';
        VARIABLE TD_DQ0_WENeg          : VitalTimingDataType;

        VARIABLE Tviol_CENeg_RESETNeg  : X01 := '0';
        VARIABLE TD_CENeg_RESETNeg     : VitalTimingDataType;

        VARIABLE Tviol_OENeg_RESETNeg  : X01 := '0';
        VARIABLE TD_OENeg_RESETNeg     : VitalTimingDataType;

        VARIABLE Tviol_WENeg_RESETNeg  : X01 := '0';
        VARIABLE TD_WENeg_RESETNeg     : VitalTimingDataType;

        VARIABLE Tviol_CENeg_WENeg_F   : X01 := '0';
        VARIABLE TD_CENeg_WENeg_F      : VitalTimingDataType;

        VARIABLE Tviol_CENeg_WENeg_R   : X01 := '0';
        VARIABLE TD_CENeg_WENeg_R      : VitalTimingDataType;

        VARIABLE Tviol_OENeg_WENeg_F   : X01 := '0';
        VARIABLE TD_OENeg_WENeg_F      : VitalTimingDataType;

        VARIABLE Tviol_OENeg_WENeg_R   : X01 := '0';
        VARIABLE TD_OENeg_WENeg_R      : VitalTimingDataType;

        VARIABLE Tviol_WENeg_CENeg_F   : X01 := '0';
        VARIABLE TD_WENeg_CENeg_F      : VitalTimingDataType;

        VARIABLE Tviol_WENeg_CENeg_R   : X01 := '0';