📄 am29lv160d.vhd
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-------------------------------------------------------------------------------- File name : am29lv160d.vhd--------------------------------------------------------------------------------- Copyright (C) 2003, 2004 Free Model Foundry; http://eda.org/fmf/---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- MODIFICATION HISTORY :---- version: | author: | mod date: | changes made:-- V1.0 J.Bogosavljevic 03 Aug 29 Initial release-- V1.1 J.Bogosavljevic 03 Oct 31 Changed VitalPathDelay01Z,-- pulse watch-- V1.2 J.Bogosavljevic 04 Jan 19 RY changend to open drain-- memory preload modified-- V1.3 J.Bogosavljevic 04 Apr 29 - elapsed_erase timer suspended as-- soon as erase suspend command issued-- - CTMOUT bug fix--------------------------------------------------------------------------------- PART DESCRIPTION:---- Library: AMD-- Technology: Flash Memory-- Part: am29lv160d---- Description: 16Mbit(2M x 8-Bit/1M x 16-Bit) CMOS Boot Sector Flash Memory-- Boot sector determined by TimingModel generic----------------------------------------------------------------------------------- Known Bugs:---------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL;LIBRARY FMF; USE FMF.gen_utils.all; USE FMF.conversions.all;--------------------------------------------------------------------------------- ENTITY DECLARATION-------------------------------------------------------------------------------ENTITY am29lv160d IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; --address tipd_A10 : VitalDelayType01 := VitalZeroDelay01; --lines tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A18 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A19 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- DQ15/A-1 tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BYTENeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_RESETNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; tpd_A0_DQ0 : VitalDelayType01 := UnitDelay01;--tACC tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tCE,tCE,tDF,-,tDF,-) tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tOE,tOE,tDF,-,tDF,-) tpd_WENeg_RY : VitalDelayType01 := UnitDelay01;--tBUSY tpd_BYTENeg_DQ15 : VitalDelayType01Z := UnitDelay01Z; --(tfhqa:-:-, tfhqa,-:-, -:-:tflqz, tfhqa:-:-:, -:-:tflqz, tfhqa:-:-:) --tsetup values tsetup_A0_CENeg : VitalDelayType := UnitDelay; --tAS edge \ tsetup_DQ0_CENeg : VitalDelayType := UnitDelay; --tDS edge / tsetup_OENeg_WENeg : VitalDelayType := UnitDelay; --0,edge / tsetup_CENeg_WENeg : VitalDelayType := UnitDelay; --0 ns / --thold values thold_A0_CENeg : VitalDelayType := UnitDelay; --tAH edge \ thold_DQ0_CENeg : VitalDelayType := UnitDelay; --tDH edge / thold_OENeg_WENeg : VitalDelayType := UnitDelay; --10,toeh,edge / thold_CENeg_WENeg : VitalDelayType := UnitDelay; --tGHVL edge / thold_CENeg_RESETNeg: VitalDelayType := UnitDelay; --tRH edge / thold_BYTENeg_CENeg : VitalDelayType := UnitDelay; --telfh, tehfl --tpw values: pulse width tpw_RESETNeg_negedge: VitalDelayType := UnitDelay; --tRP-- tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP tpw_WENeg_posedge : VitalDelayType := UnitDelay; --tWPH tpw_A0_negedge : VitalDelayType := UnitDelay; --tWC tRC(90-70) -- tdevice values: values for internal delays --Program Operation --byte write tdevice_POB : VitalDelayType := 5 us; --word write tdevice_POW : VitalDelayType := 7 us; --Sector Erase Operation tWHWH2 tdevice_SEO : VitalDelayType := 700 ms; --Timing Limit Exceeded tdevice_HANG : VitalDelayType := 400 ms; --program/erase suspend timeout tdevice_START_T1 : VitalDelayType := 20 us; --sector erase command sequence timeout tdevice_CTMOUT : VitalDelayType := 50 us; --device ready after Hardware reset(during embeded algorithm) tdevice_READY : VitalDelayType := 20 us; --tReady -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING := "none";--"am29lv160dt.mem"; prot_file_name : STRING := "none";--"am29lv160dt_prot.mem"; UserPreload : BOOLEAN := FALSE;--TRUE; LongTimming : BOOLEAN := TRUE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel --"am29lv160dt-70" ); PORT ( A19 : IN std_ulogic := 'U'; -- A18 : IN std_ulogic := 'U'; -- A17 : IN std_ulogic := 'U'; -- A16 : IN std_ulogic := 'U'; -- A15 : IN std_ulogic := 'U'; -- A14 : IN std_ulogic := 'U'; -- A13 : IN std_ulogic := 'U'; --address A12 : IN std_ulogic := 'U'; --lines A11 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A8 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- A6 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A1 : IN std_ulogic := 'U'; -- A0 : IN std_ulogic := 'U'; -- DQ15 : INOUT std_ulogic := 'U'; -- DQ15/A-1 DQ14 : INOUT std_ulogic := 'U'; -- DQ13 : INOUT std_ulogic := 'U'; -- DQ12 : INOUT std_ulogic := 'U'; -- DQ11 : INOUT std_ulogic := 'U'; -- DQ10 : INOUT std_ulogic := 'U'; -- DQ9 : INOUT std_ulogic := 'U'; -- data DQ8 : INOUT std_ulogic := 'U'; -- lines DQ7 : INOUT std_ulogic := 'U'; -- DQ6 : INOUT std_ulogic := 'U'; -- DQ5 : INOUT std_ulogic := 'U'; -- DQ4 : INOUT std_ulogic := 'U'; -- DQ3 : INOUT std_ulogic := 'U'; -- DQ2 : INOUT std_ulogic := 'U'; -- DQ1 : INOUT std_ulogic := 'U'; -- DQ0 : INOUT std_ulogic := 'U'; -- CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; BYTENeg : IN std_ulogic := 'U'; RY : OUT std_ulogic := 'U' --RY/BY# ); ATTRIBUTE VITAL_LEVEL0 of am29lv160d : ENTITY IS TRUE;END am29lv160d;--------------------------------------------------------------------------------- ARCHITECTURE DECLARATION-------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of am29lv160d IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT PartID : STRING := "am29lv160d"; CONSTANT MaxData : NATURAL := 16#FF#; --255; CONSTANT SecSize : NATURAL := 16#FFFF#; --65535 CONSTANT MemSize : NATURAL := 16#1FFFFF#; CONSTANT SecNum : NATURAL := 31; CONSTANT SubSecNum : NATURAL := 3; CONSTANT HiAddrBit : NATURAL := 19; -- interconnect path delay signals SIGNAL A19_ipd : std_ulogic := 'U'; SIGNAL A18_ipd : std_ulogic := 'U'; SIGNAL A17_ipd : std_ulogic := 'U'; SIGNAL A16_ipd : std_ulogic := 'U'; SIGNAL A15_ipd : std_ulogic := 'U'; SIGNAL A14_ipd : std_ulogic := 'U'; SIGNAL A13_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL CENeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; SIGNAL BYTENeg_ipd : std_ulogic := 'U'; --- internal delays SIGNAL POB_in : std_ulogic := '0'; SIGNAL POB_out : std_ulogic := '0'; SIGNAL POW_in : std_ulogic := '0'; SIGNAL POW_out : std_ulogic := '0'; SIGNAL SEO_in : std_ulogic := '0'; SIGNAL SEO_out : std_ulogic := '0'; SIGNAL HANG_out : std_ulogic := '0'; --Program/Erase Timing Limit SIGNAL HANG_in : std_ulogic := '0'; SIGNAL START_T1_out : std_ulogic := '0'; --Start TimeOut; SUSPEND SIGNAL START_T1_in : std_ulogic := '0'; SIGNAL CTMOUT_out : std_ulogic := '0'; --Sector Erase TimeOut SIGNAL CTMOUT_in : std_ulogic := '0'; SIGNAL READY_in : std_ulogic := '0'; SIGNAL READY_out : std_ulogic := '0'; -- Device ready after resetBEGIN --------------------------------------------------------------------------- -- Internal Delays --------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays POB :VitalBuf(POB_out, POB_in, (tdevice_POB ,UnitDelay)); POW :VitalBuf(POW_out, POW_in, (tdevice_POW ,UnitDelay)); SEO :VitalBuf(SEO_out, SEO_in, (tdevice_SEO ,UnitDelay)); HANG :VitalBuf(HANG_out,HANG_in, (tdevice_HANG ,UnitDelay)); START_T1 :VitalBuf(START_T1_out,START_T1_in,(tdevice_START_T1,UnitDelay)); CTMOUT :VitalBuf(CTMOUT_out, CTMOUT_in, (tdevice_CTMOUT-5 ns ,UnitDelay)); READY :VitalBuf(READY_out, READY_in, (tdevice_READY ,UnitDelay)); --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_0 : VitalWireDelay (A19_ipd, A19, tipd_A19); w_1 : VitalWireDelay (A18_ipd, A18, tipd_A18); w_2 : VitalWireDelay (A17_ipd, A17, tipd_A17); w_3 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_4 : VitalWireDelay (A15_ipd, A15, tipd_A15); w_5 : VitalWireDelay (A14_ipd, A14, tipd_A14); w_6 : VitalWireDelay (A13_ipd, A13, tipd_A13); w_7 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_8 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_9 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_10 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_11 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_12 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_13 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_14 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_15 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_16 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_17 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_18 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_19 : VitalWireDelay (A0_ipd, A0, tipd_A0);⌨️ 快捷键说明
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