display.vhd

来自「电子课程设计数字钟的源代码」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
entity DISPLAY is
   port(d:in std_logic_vector(3 downto 0);----连接seltime扫描部分d信号
        q:out std_logic_vector(6 downto 0));----输出段选信号（电平）
end DISPLAY;
architecture disp_are of DISPLAY is
begin
     process(d)
       begin

case d is
    when"0000" =>q<="0111111";--显示0
    when"0001" =>q<="0000110";--显示1
    when"0010" =>q<="1011011";--显示2
    when"0011" =>q<="1001111";--显示3
    when"0100" =>q<="1100110";--显示4
    when"0101" =>q<="1101101";--显示5
    when"0110" =>q<="1111101";--显示6
    when"0111" =>q<="0100111";--显示7
    when"1000" =>q<="1111111";--显示8
    when others =>q<="1101111";--显示9
end case;
  end process;
end disp_are;