yiqianfp.vhd

来自「电子课程设计数字钟的源代码」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity yiqianfp is
port (
CLK,rst: IN STD_LOGIC;
CNT: OUT STD_LOGIC);
end yiqianfp;

architecture fenpin of yiqianfp is
begin
 process(CLK ,rst)
   variable qn : integer range 999 downto 0;
 begin
   if rst='0' then 
       qn:=0;
   elsif CLK'event and CLK='1' then
     if qn<999 then
        qn:=qn+1;
     else qn:=0;
     end if;
   end if;
   if qn= 999 then CNT <='1';
     else CNT <= '0';
   end if;
 end process;
end fenpin;