counter10.vhd

VHDL的数字电子钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;

entity counter10 is 
port(clk: in std_logic;
      en: in std_logic;
      output: out std_logic);
end counter10;
architecture a of counter10 is
signal temp:std_logic_vector(3 downto 0);
begin
p1:process(clk)
  begin
    if(temp<"0101")then output<='0';
     elsif(temp<"1000")then output<='1';
     else output<='1';
     end if;
  end process;
 p2:process(clk,en)
  begin 
     if(en='1')then temp<="0000";
     elsif(clk'event and clk='1')then 
      if(temp="1001")then temp<="0000";
       else temp<=temp+1;
      end if; 
     end if;
   end process;   
end a;