baoshiqi.vhd

来自「VHDL的数字电子钟程序」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity baoshiqi is
port(clk1000:in std_logic;
     clk500:in std_logic;
     en: in std_logic;
     kz_du:in std_logic;
     kz_di:in std_logic;
     kz_nz:in std_logic;
     kz: out std_logic);
end baoshiqi;
architecture a of baoshiqi is
signal t:std_logic;
begin
p1:process(kz_nz)
  begin
   if(en='1')then t<='0';
   else t<=kz_nz;
   end if;
  end process;
p2:process(kz_di,kz_du,t)
  begin
   if(kz_di='1')then kz<=clk1000;
    elsif(kz_du='1')then kz<=clk500;
     elsif(t='1')then kz<=clk1000;
      else kz<='0';
   end if;
 end process;
end a;