zhongbiao.vhd

VHDL的数字电子钟程序

----------------------zhu cheng xu--------------------------
----- 顶层电路-------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity zhongbiao is
port(clk: in std_logic;
     clk_tiao1: in std_logic;
     clk_tiao2: in std_logic;
     a: in std_logic;
     b: in std_logic;
     c: in std_logic;
     d: in std_logic;
     kz: out std_logic;
     BT:  out std_logic_vector(7 downto 0);
     SG: out std_logic_vector(7 downto 0)
   );
end zhongbiao;
architecture a of zhongbiao is
component bszz 
port(clk1000:in std_logic;
     clk500:in std_logic;
     en: in std_logic;
     s_h: in std_logic_vector(3 downto 0);
     s_l: in std_logic_vector(3 downto 0);
     f_h: in std_logic_vector(3 downto 0);
     f_l: in std_logic_vector(3 downto 0);
     m_h: in std_logic_vector(3 downto 0);
     m_l: in std_logic_vector(3 downto 0);
     p_h: in std_logic_vector(3 downto 0);
     h1 : in std_logic_vector(3 downto 0);
     h2 : in std_logic_vector(3 downto 0);
     f1 : in std_logic_vector(3 downto 0);
     f2 : in std_logic_vector(3 downto 0);
     kz: out std_logic);
end component;

component fenpinqi 
port(clk:in std_logic;
     clk_500hz:out std_logic;
     clk_1hz:out std_logic;
     pm_h: out std_logic_vector(3 downto 0);
     pm_l:  out std_logic_vector(3 downto 0));
end component;

component kzyima 
port(a: in std_logic;
     b: in std_logic;
     c: in std_logic;
     mx: out std_logic;
     en: out std_logic;
     tx: out std_logic;
     k1: out std_logic;
     k2: out std_logic);
end component;
component sheding 
port(clk_tiao: in std_logic;
      tx: in std_logic;
      en: in std_logic;
      h_high: out std_logic_vector(3 downto 0);
      h_low:  out std_logic_vector(3 downto 0);
      m_high: out std_logic_vector(3 downto 0);
      m_low:  out std_logic_vector(3 downto 0);
      s_high: out std_logic_vector(3 downto 0);
      s_low:  out std_logic_vector(3 downto 0));
end component;
component shijian
port(clk: in std_logic;
     clk_tiao: in std_logic;
     kz1: in std_logic;
     kz2: in std_logic;
     day: out std_logic;
     day_y: out std_logic;
     shi_high:  out std_logic_vector(3 downto 0);
     shi_low:   out std_logic_vector(3 downto 0);
     fen_high:  out std_logic_vector(3 downto 0);
     fen_low:   out std_logic_vector(3 downto 0);
     miao_high: out std_logic_vector(3 downto 0);
     miao_low:  out std_logic_vector(3 downto 0));
end component;
component xsxuanze 
port(h_high : in std_logic_vector(3 downto 0);
     h_low : in std_logic_vector(3 downto 0);
     m_high : in std_logic_vector(3 downto 0);
     m_low : in std_logic_vector(3 downto 0);
     s_high: in std_logic_vector(3 downto 0);
     s_low: in std_logic_vector(3 downto 0);
     sdh_high : in std_logic_vector(3 downto 0);
     sdh_low : in std_logic_vector(3 downto 0);
     sdm_high : in std_logic_vector(3 downto 0);
     sdm_low : in std_logic_vector(3 downto 0);
     sds_high: in std_logic_vector(3 downto 0);
     sds_low: in std_logic_vector(3 downto 0);
     en : in std_logic;
     clk: in std_logic;
     --x1 : out std_logic_vector(3 downto 0);
     --x2 : out std_logic_vector(3 downto 0);
     --y1 : out std_logic_vector(3 downto 0);
     --y2 : out std_logic_vector(3 downto 0);
     BT:  out std_logic_vector(7 downto 0);
     SG:  out std_logic_vector(7 downto 0));
end component;
component pbclk  
port(a: in std_logic;
     b: in std_logic;
     c: in std_logic;
     cp: in std_logic;
     clk: out std_logic);
end component;
signal h1,h2,m1,m2,s1,s2,h_1,h_2,m_1,m_2,s_1,s_2: std_logic_vector(3 downto 0);
signal mx,en,tx,k1,k2,cp: std_logic;
signal day,day_y,clk_100: std_logic;
signal p1,p2:std_logic_vector(3 downto 0);
signal x1,x2,x:std_logic;
signal clk_1,clk_500:std_logic;
begin
 u1:kzyima port map(a,b,c,mx,en,tx,k1,k2);
 u2:xsxuanze port map(h1,h2,m1,m2,s1,s2,
                      h_1,h_2,m_1,m_2,s_1,s_2,
                      mx,en,
                      BT,SG
                      );
 u3:sheding port map(clk_tiao2,tx,en,h_1,h_2,m_1,m_2,s_1,s_2);
 u4:bszz port map(clk,clk_500,d,h1,h2,m1,m2,s1,s2,p1,
                      h_1,h_2,m_1,m_2,kz);
 u5:shijian port map(cp,clk_tiao1,k1,k2,day,day_y,h1,h2,m1,m2,s1,s2);
 u6:pbclk port map(a,b,c,clk_1,cp);
 u7:fenpinqi port map(clk,clk_500,clk_1,p1,p2);
 
 end a;