float.tan.rpt

该文档是基于QUARTUS2_6.0的Verilog试验例程

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 15 16:42:07 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off float -c float --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "clkx" is an undefined clock
Info: Clock "clk" has Internal fmax of 249.94 MHz between source register "saomiao:inst|data0[0]" and destination memory "zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4" (period= 4.001 ns)
    Info: + Longest register to memory delay is 3.708 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y3_N0; Fanout = 8; REG Node = 'saomiao:inst|data0[0]'
        Info: 2: + IC(0.558 ns) + CELL(0.423 ns) = 0.981 ns; Loc. = LC_X12_Y3_N1; Fanout = 2; COMB Node = 'hdf:inst1|y[0]~13'
        Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.059 ns; Loc. = LC_X12_Y3_N2; Fanout = 2; COMB Node = 'hdf:inst1|y[1]~15'
        Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.137 ns; Loc. = LC_X12_Y3_N3; Fanout = 2; COMB Node = 'hdf:inst1|y[2]~17'
        Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.315 ns; Loc. = LC_X12_Y3_N4; Fanout = 2; COMB Node = 'hdf:inst1|y[3]~19'
        Info: 6: + IC(0.000 ns) + CELL(0.621 ns) = 1.936 ns; Loc. = LC_X12_Y3_N5; Fanout = 1; COMB Node = 'hdf:inst1|y[4]~20'
        Info: 7: + IC(1.389 ns) + CELL(0.383 ns) = 3.708 ns; Loc. = M4K_X13_Y3; Fanout = 16; MEM Node = 'zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4'
        Info: Total cell delay = 1.761 ns ( 47.49 % )
        Info: Total interconnect delay = 1.947 ns ( 52.51 % )
    Info: - Smallest clock skew is 0.024 ns
        Info: + Shortest clock path from clock "clk" to destination memory is 2.754 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clk'
            Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y3; Fanout = 16; MEM Node = 'zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4'
            Info: Total cell delay = 2.191 ns ( 79.56 % )
            Info: Total interconnect delay = 0.563 ns ( 20.44 % )
        Info: - Longest clock path from clock "clk" to source register is 2.730 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clk'
            Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X12_Y3_N0; Fanout = 8; REG Node = 'saomiao:inst|data0[0]'
            Info: Total cell delay = 2.180 ns ( 79.85 % )
            Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.093 ns
Info: Clock "clkx" Internal fmax is restricted to 275.03 MHz between source register "shj:inst7|data2[0]" and destination register "shj:inst7|data2[4]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.264 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y3_N1; Fanout = 6; REG Node = 'shj:inst7|data2[0]'
            Info: 2: + IC(0.527 ns) + CELL(0.564 ns) = 1.091 ns; Loc. = LC_X15_Y3_N1; Fanout = 2; COMB Node = 'shj:inst7|data2[0]~268'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.169 ns; Loc. = LC_X15_Y3_N2; Fanout = 2; COMB Node = 'shj:inst7|data2[1]~269'
            Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.247 ns; Loc. = LC_X15_Y3_N3; Fanout = 2; COMB Node = 'shj:inst7|data2[2]~270'
            Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.425 ns; Loc. = LC_X15_Y3_N4; Fanout = 2; COMB Node = 'shj:inst7|data2[3]~271'
            Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.264 ns; Loc. = LC_X15_Y3_N5; Fanout = 6; REG Node = 'shj:inst7|data2[4]'
            Info: Total cell delay = 1.737 ns ( 76.72 % )
            Info: Total interconnect delay = 0.527 ns ( 23.28 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clkx" to destination register is 2.743 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'clkx'
                Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y3_N5; Fanout = 6; REG Node = 'shj:inst7|data2[4]'
                Info: Total cell delay = 2.180 ns ( 79.48 % )
                Info: Total interconnect delay = 0.563 ns ( 20.52 % )
            Info: - Longest clock path from clock "clkx" to source register is 2.743 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'clkx'
                Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y3_N1; Fanout = 6; REG Node = 'shj:inst7|data2[0]'
                Info: Total cell delay = 2.180 ns ( 79.48 % )
                Info: Total interconnect delay = 0.563 ns ( 20.52 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "shj:inst7|data2[0]" (data pin = "clr", clock pin = "clkx") is 5.753 ns
    Info: + Longest pin to register delay is 8.459 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_58; Fanout = 7; PIN Node = 'clr'
        Info: 2: + IC(5.365 ns) + CELL(0.292 ns) = 7.132 ns; Loc. = LC_X15_Y3_N9; Fanout = 6; COMB Node = 'shj:inst7|data2[5]~274'
        Info: 3: + IC(0.460 ns) + CELL(0.867 ns) = 8.459 ns; Loc. = LC_X15_Y3_N1; Fanout = 6; REG Node = 'shj:inst7|data2[0]'
        Info: Total cell delay = 2.634 ns ( 31.14 % )
        Info: Total interconnect delay = 5.825 ns ( 68.86 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clkx" to destination register is 2.743 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'clkx'
        Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y3_N1; Fanout = 6; REG Node = 'shj:inst7|data2[0]'
        Info: Total cell delay = 2.180 ns ( 79.48 % )
        Info: Total interconnect delay = 0.563 ns ( 20.52 % )
Info: tco from clock "clk" to destination pin "out[10]" through memory "zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0" is 12.555 ns
    Info: + Longest clock path from clock "clk" to source memory is 2.754 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y3; Fanout = 16; MEM Node = 'zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0'
        Info: Total cell delay = 2.191 ns ( 79.56 % )
        Info: Total interconnect delay = 0.563 ns ( 20.44 % )
    Info: + Micro clock to output delay of source is 0.650 ns
    Info: + Longest memory to pin delay is 9.151 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y3; Fanout = 16; MEM Node = 'zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y3; Fanout = 1; MEM Node = 'zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|q_a[10]'
        Info: 3: + IC(2.735 ns) + CELL(2.108 ns) = 9.151 ns; Loc. = PIN_127; Fanout = 0; PIN Node = 'out[10]'
        Info: Total cell delay = 6.416 ns ( 70.11 % )
        Info: Total interconnect delay = 2.735 ns ( 29.89 % )
Info: th for register "shj:inst7|data2[1]" (data pin = "control", clock pin = "clkx") is -1.333 ns
    Info: + Longest clock path from clock "clkx" to destination register is 2.743 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'clkx'
        Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y3_N2; Fanout = 6; REG Node = 'shj:inst7|data2[1]'
        Info: Total cell delay = 2.180 ns ( 79.48 % )
        Info: Total interconnect delay = 0.563 ns ( 20.52 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 4.091 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 12; PIN Node = 'control'
        Info: 2: + IC(2.015 ns) + CELL(0.607 ns) = 4.091 ns; Loc. = LC_X15_Y3_N2; Fanout = 6; REG Node = 'shj:inst7|data2[1]'
        Info: Total cell delay = 2.076 ns ( 50.75 % )
        Info: Total interconnect delay = 2.015 ns ( 49.25 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Nov 15 16:42:07 2007
    Info: Elapsed time: 00:00:01