float.hier_info

该文档是基于QUARTUS2_6.0的Verilog试验例程

|float
out[0] <= zimo:inst4.q[0]
out[1] <= zimo:inst4.q[1]
out[2] <= zimo:inst4.q[2]
out[3] <= zimo:inst4.q[3]
out[4] <= zimo:inst4.q[4]
out[5] <= zimo:inst4.q[5]
out[6] <= zimo:inst4.q[6]
out[7] <= zimo:inst4.q[7]
out[8] <= zimo:inst4.q[8]
out[9] <= zimo:inst4.q[9]
out[10] <= zimo:inst4.q[10]
out[11] <= zimo:inst4.q[11]
out[12] <= zimo:inst4.q[12]
out[13] <= zimo:inst4.q[13]
out[14] <= zimo:inst4.q[14]
out[15] <= zimo:inst4.q[15]
clk => zimo:inst4.clock
clk => saomiao:inst.clk0
clkx => shj:inst7.clk2
clr => shj:inst7.clr
stop => shj:inst7.stop
control => shj:inst7.control_1
xuanze[0] <= saomiao:inst.data0[0]
xuanze[1] <= saomiao:inst.data0[1]
xuanze[2] <= saomiao:inst.data0[2]
xuanze[3] <= saomiao:inst.data0[3]


|float|zimo:inst4
address[0] => address[0]~5.IN1
address[1] => address[1]~4.IN1
address[2] => address[2]~3.IN1
address[3] => address[3]~2.IN1
address[4] => address[4]~1.IN1
address[5] => address[5]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a
q[14] <= altsyncram:altsyncram_component.q_a
q[15] <= altsyncram:altsyncram_component.q_a


|float|zimo:inst4|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_d651:auto_generated.address_a[0]
address_a[1] => altsyncram_d651:auto_generated.address_a[1]
address_a[2] => altsyncram_d651:auto_generated.address_a[2]
address_a[3] => altsyncram_d651:auto_generated.address_a[3]
address_a[4] => altsyncram_d651:auto_generated.address_a[4]
address_a[5] => altsyncram_d651:auto_generated.address_a[5]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_d651:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_d651:auto_generated.q_a[0]
q_a[1] <= altsyncram_d651:auto_generated.q_a[1]
q_a[2] <= altsyncram_d651:auto_generated.q_a[2]
q_a[3] <= altsyncram_d651:auto_generated.q_a[3]
q_a[4] <= altsyncram_d651:auto_generated.q_a[4]
q_a[5] <= altsyncram_d651:auto_generated.q_a[5]
q_a[6] <= altsyncram_d651:auto_generated.q_a[6]
q_a[7] <= altsyncram_d651:auto_generated.q_a[7]
q_a[8] <= altsyncram_d651:auto_generated.q_a[8]
q_a[9] <= altsyncram_d651:auto_generated.q_a[9]
q_a[10] <= altsyncram_d651:auto_generated.q_a[10]
q_a[11] <= altsyncram_d651:auto_generated.q_a[11]
q_a[12] <= altsyncram_d651:auto_generated.q_a[12]
q_a[13] <= altsyncram_d651:auto_generated.q_a[13]
q_a[14] <= altsyncram_d651:auto_generated.q_a[14]
q_a[15] <= altsyncram_d651:auto_generated.q_a[15]
q_b[0] <= <GND>


|float|zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT


|float|hdf:inst1
a1[0] => Add0.IN6
a1[1] => Add0.IN5
a1[2] => Add0.IN4
a1[3] => Add0.IN3
a2[0] => Add0.IN12
a2[1] => Add0.IN11
a2[2] => Add0.IN10
a2[3] => Add0.IN9
a2[4] => Add0.IN8
a2[5] => Add0.IN7
y[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
y[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
y[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
y[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|float|saomiao:inst
clk0 => data0[2]~reg0.CLK
clk0 => data0[1]~reg0.CLK
clk0 => data0[0]~reg0.CLK
clk0 => data0[3]~reg0.CLK
data0[0] <= data0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data0[1] <= data0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data0[2] <= data0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data0[3] <= data0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|float|shj:inst7
clk2 => data2[4]~reg0.CLK
clk2 => data2[3]~reg0.CLK
clk2 => data2[2]~reg0.CLK
clk2 => data2[1]~reg0.CLK
clk2 => data2[0]~reg0.CLK
clk2 => data2[5]~reg0.CLK
clr => data2~12.OUTPUTSELECT
clr => data2~13.OUTPUTSELECT
clr => data2~14.OUTPUTSELECT
clr => data2~15.OUTPUTSELECT
clr => data2~16.OUTPUTSELECT
clr => data2~17.OUTPUTSELECT
stop => data2~6.OUTPUTSELECT
stop => data2~7.OUTPUTSELECT
stop => data2~8.OUTPUTSELECT
stop => data2~9.OUTPUTSELECT
stop => data2~10.OUTPUTSELECT
stop => data2~11.OUTPUTSELECT
control_1 => data2~0.OUTPUTSELECT
control_1 => data2~1.OUTPUTSELECT
control_1 => data2~2.OUTPUTSELECT
control_1 => data2~3.OUTPUTSELECT
control_1 => data2~4.OUTPUTSELECT
control_1 => data2~5.OUTPUTSELECT
data2[0] <= data2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data2[1] <= data2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data2[2] <= data2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data2[3] <= data2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data2[4] <= data2[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data2[5] <= data2[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE