📄 float.tan.qmsg

📁 该文档是基于QUARTUS2_6.0的Verilog试验例程
💻 QMSG
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{ "Info" "ITDB_TSU_RESULT" "shj:inst7\|data2\[0\] clr clkx 5.753 ns register " "Info: tsu for register \"shj:inst7\|data2\[0\]\" (data pin = \"clr\", clock pin = \"clkx\") is 5.753 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.459 ns + Longest pin register " "Info: + Longest pin to register delay is 8.459 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clr 1 PIN PIN_58 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_58; Fanout = 7; PIN Node = 'clr'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 232 56 224 248 "clr" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.365 ns) + CELL(0.292 ns) 7.132 ns shj:inst7\|data2\[5\]~274 2 COMB LC_X15_Y3_N9 6 " "Info: 2: + IC(5.365 ns) + CELL(0.292 ns) = 7.132 ns; Loc. = LC_X15_Y3_N9; Fanout = 6; COMB Node = 'shj:inst7\|data2\[5\]~274'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.657 ns" { clr shj:inst7|data2[5]~274 } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.460 ns) + CELL(0.867 ns) 8.459 ns shj:inst7\|data2\[0\] 3 REG LC_X15_Y3_N1 6 " "Info: 3: + IC(0.460 ns) + CELL(0.867 ns) = 8.459 ns; Loc. = LC_X15_Y3_N1; Fanout = 6; REG Node = 'shj:inst7\|data2\[0\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.327 ns" { shj:inst7|data2[5]~274 shj:inst7|data2[0] } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.634 ns ( 31.14 % ) " "Info: Total cell delay = 2.634 ns ( 31.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.825 ns ( 68.86 % ) " "Info: Total interconnect delay = 5.825 ns ( 68.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.459 ns" { clr shj:inst7|data2[5]~274 shj:inst7|data2[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.459 ns" { clr clr~out0 shj:inst7|data2[5]~274 shj:inst7|data2[0] } { 0.000ns 0.000ns 5.365ns 0.460ns } { 0.000ns 1.475ns 0.292ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx destination 2.743 ns - Shortest register " "Info: - Shortest clock path from clock \"clkx\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx 1 CLK PIN_16 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'clkx'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clkx } "NODE_NAME" } } { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 216 56 224 232 "clkx" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns shj:inst7\|data2\[0\] 2 REG LC_X15_Y3_N1 6 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y3_N1; Fanout = 6; REG Node = 'shj:inst7\|data2\[0\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.274 ns" { clkx shj:inst7|data2[0] } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clkx shj:inst7|data2[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.743 ns" { clkx clkx~out0 shj:inst7|data2[0] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.459 ns" { clr shj:inst7|data2[5]~274 shj:inst7|data2[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.459 ns" { clr clr~out0 shj:inst7|data2[5]~274 shj:inst7|data2[0] } { 0.000ns 0.000ns 5.365ns 0.460ns } { 0.000ns 1.475ns 0.292ns 0.867ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clkx shj:inst7|data2[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.743 ns" { clkx clkx~out0 shj:inst7|data2[0] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out\[10\] zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg0 12.555 ns memory " "Info: tco from clock \"clk\" to destination pin \"out\[10\]\" through memory \"zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg0\" is 12.555 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.754 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 88 64 232 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.722 ns) 2.754 ns zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg0 2 MEM M4K_X13_Y3 16 " "Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y3; Fanout = 16; MEM Node = 'zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg0'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.285 ns" { clk zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_d651.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/db/altsyncram_d651.tdf" 328 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 79.56 % ) " "Info: Total cell delay = 2.191 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.754 ns" { clk zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_d651.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/db/altsyncram_d651.tdf" 328 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.151 ns + Longest memory pin " "Info: + Longest memory to pin delay is 9.151 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg0 1 MEM M4K_X13_Y3 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y3; Fanout = 16; MEM Node = 'zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg0'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_d651.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/db/altsyncram_d651.tdf" 328 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|q_a\[10\] 2 MEM M4K_X13_Y3 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y3; Fanout = 1; MEM Node = 'zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|q_a\[10\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "4.308 ns" { zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|q_a[10] } "NODE_NAME" } } { "db/altsyncram_d651.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/db/altsyncram_d651.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.735 ns) + CELL(2.108 ns) 9.151 ns out\[10\] 3 PIN PIN_127 0 " "Info: 3: + IC(2.735 ns) + CELL(2.108 ns) = 9.151 ns; Loc. = PIN_127; Fanout = 0; PIN Node = 'out\[10\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "4.843 ns" { zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|q_a[10] out[10] } "NODE_NAME" } } { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 160 712 888 176 "out\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.416 ns ( 70.11 % ) " "Info: Total cell delay = 6.416 ns ( 70.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.735 ns ( 29.89 % ) " "Info: Total interconnect delay = 2.735 ns ( 29.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "9.151 ns" { zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|q_a[10] out[10] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "9.151 ns" { zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|q_a[10] out[10] } { 0.000ns 0.000ns 2.735ns } { 0.000ns 4.308ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.754 ns" { clk zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "9.151 ns" { zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|q_a[10] out[10] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "9.151 ns" { zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg0 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|q_a[10] out[10] } { 0.000ns 0.000ns 2.735ns } { 0.000ns 4.308ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "shj:inst7\|data2\[1\] control clkx -1.333 ns register " "Info: th for register \"shj:inst7\|data2\[1\]\" (data pin = \"control\", clock pin = \"clkx\") is -1.333 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx destination 2.743 ns + Longest register " "Info: + Longest clock path from clock \"clkx\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx 1 CLK PIN_16 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'clkx'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clkx } "NODE_NAME" } } { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 216 56 224 232 "clkx" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns shj:inst7\|data2\[1\] 2 REG LC_X15_Y3_N2 6 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y3_N2; Fanout = 6; REG Node = 'shj:inst7\|data2\[1\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.274 ns" { clkx shj:inst7|data2[1] } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clkx shj:inst7|data2[1] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.743 ns" { clkx clkx~out0 shj:inst7|data2[1] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.091 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.091 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns control 1 PIN PIN_93 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 12; PIN Node = 'control'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { control } "NODE_NAME" } } { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 264 56 224 280 "control" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.015 ns) + CELL(0.607 ns) 4.091 ns shj:inst7\|data2\[1\] 2 REG LC_X15_Y3_N2 6 " "Info: 2: + IC(2.015 ns) + CELL(0.607 ns) = 4.091 ns; Loc. = LC_X15_Y3_N2; Fanout = 6; REG Node = 'shj:inst7\|data2\[1\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.622 ns" { control shj:inst7|data2[1] } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns ( 50.75 % ) " "Info: Total cell delay = 2.076 ns ( 50.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.015 ns ( 49.25 % ) " "Info: Total interconnect delay = 2.015 ns ( 49.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "4.091 ns" { control shj:inst7|data2[1] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "4.091 ns" { control control~out0 shj:inst7|data2[1] } { 0.000ns 0.000ns 2.015ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clkx shj:inst7|data2[1] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.743 ns" { clkx clkx~out0 shj:inst7|data2[1] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "4.091 ns" { control shj:inst7|data2[1] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "4.091 ns" { control control~out0 shj:inst7|data2[1] } { 0.000ns 0.000ns 2.015ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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