float.tan.qmsg

该文档是基于QUARTUS2_6.0的Verilog试验例程

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 88 64 232 104 "clk" "" } } } } { "d:/quartus2_setup/win/Assignment Editor.qase" "" { Assignment "d:/quartus2_setup/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clkx " "Info: Assuming node \"clkx\" is an undefined clock" {  } { { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 216 56 224 232 "clkx" "" } } } } { "d:/quartus2_setup/win/Assignment Editor.qase" "" { Assignment "d:/quartus2_setup/win/Assignment Editor.qase" 1 { { 0 "clkx" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register saomiao:inst\|data0\[0\] memory zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg4 249.94 MHz 4.001 ns Internal " "Info: Clock \"clk\" has Internal fmax of 249.94 MHz between source register \"saomiao:inst\|data0\[0\]\" and destination memory \"zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg4\" (period= 4.001 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.708 ns + Longest register memory " "Info: + Longest register to memory delay is 3.708 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns saomiao:inst\|data0\[0\] 1 REG LC_X12_Y3_N0 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y3_N0; Fanout = 8; REG Node = 'saomiao:inst\|data0\[0\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { saomiao:inst|data0[0] } "NODE_NAME" } } { "saomiao.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/saomiao.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.423 ns) 0.981 ns hdf:inst1\|y\[0\]~13 2 COMB LC_X12_Y3_N1 2 " "Info: 2: + IC(0.558 ns) + CELL(0.423 ns) = 0.981 ns; Loc. = LC_X12_Y3_N1; Fanout = 2; COMB Node = 'hdf:inst1\|y\[0\]~13'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.981 ns" { saomiao:inst|data0[0] hdf:inst1|y[0]~13 } "NODE_NAME" } } { "hdf.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/hdf.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.059 ns hdf:inst1\|y\[1\]~15 3 COMB LC_X12_Y3_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.059 ns; Loc. = LC_X12_Y3_N2; Fanout = 2; COMB Node = 'hdf:inst1\|y\[1\]~15'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { hdf:inst1|y[0]~13 hdf:inst1|y[1]~15 } "NODE_NAME" } } { "hdf.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/hdf.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.137 ns hdf:inst1\|y\[2\]~17 4 COMB LC_X12_Y3_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.137 ns; Loc. = LC_X12_Y3_N3; Fanout = 2; COMB Node = 'hdf:inst1\|y\[2\]~17'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { hdf:inst1|y[1]~15 hdf:inst1|y[2]~17 } "NODE_NAME" } } { "hdf.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/hdf.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.315 ns hdf:inst1\|y\[3\]~19 5 COMB LC_X12_Y3_N4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.315 ns; Loc. = LC_X12_Y3_N4; Fanout = 2; COMB Node = 'hdf:inst1\|y\[3\]~19'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.178 ns" { hdf:inst1|y[2]~17 hdf:inst1|y[3]~19 } "NODE_NAME" } } { "hdf.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/hdf.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 1.936 ns hdf:inst1\|y\[4\]~20 6 COMB LC_X12_Y3_N5 1 " "Info: 6: + IC(0.000 ns) + CELL(0.621 ns) = 1.936 ns; Loc. = LC_X12_Y3_N5; Fanout = 1; COMB Node = 'hdf:inst1\|y\[4\]~20'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.621 ns" { hdf:inst1|y[3]~19 hdf:inst1|y[4]~20 } "NODE_NAME" } } { "hdf.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/hdf.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.389 ns) + CELL(0.383 ns) 3.708 ns zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg4 7 MEM M4K_X13_Y3 16 " "Info: 7: + IC(1.389 ns) + CELL(0.383 ns) = 3.708 ns; Loc. = M4K_X13_Y3; Fanout = 16; MEM Node = 'zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg4'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.772 ns" { hdf:inst1|y[4]~20 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_d651.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/db/altsyncram_d651.tdf" 328 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.761 ns ( 47.49 % ) " "Info: Total cell delay = 1.761 ns ( 47.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.947 ns ( 52.51 % ) " "Info: Total interconnect delay = 1.947 ns ( 52.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "3.708 ns" { saomiao:inst|data0[0] hdf:inst1|y[0]~13 hdf:inst1|y[1]~15 hdf:inst1|y[2]~17 hdf:inst1|y[3]~19 hdf:inst1|y[4]~20 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "3.708 ns" { saomiao:inst|data0[0] hdf:inst1|y[0]~13 hdf:inst1|y[1]~15 hdf:inst1|y[2]~17 hdf:inst1|y[3]~19 hdf:inst1|y[4]~20 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } { 0.000ns 0.558ns 0.000ns 0.000ns 0.000ns 0.000ns 1.389ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.621ns 0.383ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.024 ns - Smallest " "Info: - Smallest clock skew is 0.024 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.754 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 88 64 232 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.722 ns) 2.754 ns zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg4 2 MEM M4K_X13_Y3 16 " "Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y3; Fanout = 16; MEM Node = 'zimo:inst4\|altsyncram:altsyncram_component\|altsyncram_d651:auto_generated\|ram_block1a15~porta_address_reg4'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.285 ns" { clk zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_d651.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/db/altsyncram_d651.tdf" 328 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 79.56 % ) " "Info: Total cell delay = 2.191 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.754 ns" { clk zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 88 64 232 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns saomiao:inst\|data0\[0\] 2 REG LC_X12_Y3_N0 8 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X12_Y3_N0; Fanout = 8; REG Node = 'saomiao:inst\|data0\[0\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.261 ns" { clk saomiao:inst|data0[0] } "NODE_NAME" } } { "saomiao.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/saomiao.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.730 ns" { clk saomiao:inst|data0[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 saomiao:inst|data0[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.754 ns" { clk zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.730 ns" { clk saomiao:inst|data0[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 saomiao:inst|data0[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "saomiao.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/saomiao.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_d651.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/db/altsyncram_d651.tdf" 328 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "3.708 ns" { saomiao:inst|data0[0] hdf:inst1|y[0]~13 hdf:inst1|y[1]~15 hdf:inst1|y[2]~17 hdf:inst1|y[3]~19 hdf:inst1|y[4]~20 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "3.708 ns" { saomiao:inst|data0[0] hdf:inst1|y[0]~13 hdf:inst1|y[1]~15 hdf:inst1|y[2]~17 hdf:inst1|y[3]~19 hdf:inst1|y[4]~20 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } { 0.000ns 0.558ns 0.000ns 0.000ns 0.000ns 0.000ns 1.389ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.621ns 0.383ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.754 ns" { clk zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.730 ns" { clk saomiao:inst|data0[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 saomiao:inst|data0[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clkx register register shj:inst7\|data2\[0\] shj:inst7\|data2\[4\] 275.03 MHz Internal " "Info: Clock \"clkx\" Internal fmax is restricted to 275.03 MHz between source register \"shj:inst7\|data2\[0\]\" and destination register \"shj:inst7\|data2\[4\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.264 ns + Longest register register " "Info: + Longest register to register delay is 2.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shj:inst7\|data2\[0\] 1 REG LC_X15_Y3_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y3_N1; Fanout = 6; REG Node = 'shj:inst7\|data2\[0\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { shj:inst7|data2[0] } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.527 ns) + CELL(0.564 ns) 1.091 ns shj:inst7\|data2\[0\]~268 2 COMB LC_X15_Y3_N1 2 " "Info: 2: + IC(0.527 ns) + CELL(0.564 ns) = 1.091 ns; Loc. = LC_X15_Y3_N1; Fanout = 2; COMB Node = 'shj:inst7\|data2\[0\]~268'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.091 ns" { shj:inst7|data2[0] shj:inst7|data2[0]~268 } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.169 ns shj:inst7\|data2\[1\]~269 3 COMB LC_X15_Y3_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.169 ns; Loc. = LC_X15_Y3_N2; Fanout = 2; COMB Node = 'shj:inst7\|data2\[1\]~269'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { shj:inst7|data2[0]~268 shj:inst7|data2[1]~269 } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.247 ns shj:inst7\|data2\[2\]~270 4 COMB LC_X15_Y3_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.247 ns; Loc. = LC_X15_Y3_N3; Fanout = 2; COMB Node = 'shj:inst7\|data2\[2\]~270'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { shj:inst7|data2[1]~269 shj:inst7|data2[2]~270 } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.425 ns shj:inst7\|data2\[3\]~271 5 COMB LC_X15_Y3_N4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.425 ns; Loc. = LC_X15_Y3_N4; Fanout = 2; COMB Node = 'shj:inst7\|data2\[3\]~271'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.178 ns" { shj:inst7|data2[2]~270 shj:inst7|data2[3]~271 } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.264 ns shj:inst7\|data2\[4\] 6 REG LC_X15_Y3_N5 6 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.264 ns; Loc. = LC_X15_Y3_N5; Fanout = 6; REG Node = 'shj:inst7\|data2\[4\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.839 ns" { shj:inst7|data2[3]~271 shj:inst7|data2[4] } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns ( 76.72 % ) " "Info: Total cell delay = 1.737 ns ( 76.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.527 ns ( 23.28 % ) " "Info: Total interconnect delay = 0.527 ns ( 23.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.264 ns" { shj:inst7|data2[0] shj:inst7|data2[0]~268 shj:inst7|data2[1]~269 shj:inst7|data2[2]~270 shj:inst7|data2[3]~271 shj:inst7|data2[4] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.264 ns" { shj:inst7|data2[0] shj:inst7|data2[0]~268 shj:inst7|data2[1]~269 shj:inst7|data2[2]~270 shj:inst7|data2[3]~271 shj:inst7|data2[4] } { 0.000ns 0.527ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx destination 2.743 ns + Shortest register " "Info: + Shortest clock path from clock \"clkx\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx 1 CLK PIN_16 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'clkx'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clkx } "NODE_NAME" } } { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 216 56 224 232 "clkx" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns shj:inst7\|data2\[4\] 2 REG LC_X15_Y3_N5 6 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y3_N5; Fanout = 6; REG Node = 'shj:inst7\|data2\[4\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.274 ns" { clkx shj:inst7|data2[4] } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clkx shj:inst7|data2[4] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.743 ns" { clkx clkx~out0 shj:inst7|data2[4] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx source 2.743 ns - Longest register " "Info: - Longest clock path from clock \"clkx\" to source register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx 1 CLK PIN_16 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'clkx'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clkx } "NODE_NAME" } } { "float.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/点阵/float.bdf" { { 216 56 224 232 "clkx" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns shj:inst7\|data2\[0\] 2 REG LC_X15_Y3_N1 6 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y3_N1; Fanout = 6; REG Node = 'shj:inst7\|data2\[0\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.274 ns" { clkx shj:inst7|data2[0] } "NODE_NAME" } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clkx shj:inst7|data2[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.743 ns" { clkx clkx~out0 shj:inst7|data2[0] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clkx shj:inst7|data2[4] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.743 ns" { clkx clkx~out0 shj:inst7|data2[4] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clkx shj:inst7|data2[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.743 ns" { clkx clkx~out0 shj:inst7|data2[0] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.264 ns" { shj:inst7|data2[0] shj:inst7|data2[0]~268 shj:inst7|data2[1]~269 shj:inst7|data2[2]~270 shj:inst7|data2[3]~271 shj:inst7|data2[4] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.264 ns" { shj:inst7|data2[0] shj:inst7|data2[0]~268 shj:inst7|data2[1]~269 shj:inst7|data2[2]~270 shj:inst7|data2[3]~271 shj:inst7|data2[4] } { 0.000ns 0.527ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clkx shj:inst7|data2[4] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.743 ns" { clkx clkx~out0 shj:inst7|data2[4] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clkx shj:inst7|data2[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.743 ns" { clkx clkx~out0 shj:inst7|data2[0] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { shj:inst7|data2[4] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { shj:inst7|data2[4] } {  } {  } } } { "shj.v" "" { Text "C:/Documents and Settings/Administrator/桌面/点阵/shj.v" 23 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}