float.map.rpt

该文档是基于QUARTUS2_6.0的Verilog试验例程

; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |float|shj:inst7|data2[5]  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------------------------------------------------------------------------+
; Source assignments for zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------+
; Assignment                      ; Value              ; From ; To                                 ;
+---------------------------------+--------------------+------+------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                  ;
+---------------------------------+--------------------+------+------------------------------------+


+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: zimo:inst4|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+----------------------------------+
; Parameter Name                     ; Value           ; Type                             ;
+------------------------------------+-----------------+----------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                          ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                       ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                     ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                   ;
; OPERATION_MODE                     ; ROM             ; Untyped                          ;
; WIDTH_A                            ; 16              ; Integer                          ;
; WIDTHAD_A                          ; 6               ; Integer                          ;
; NUMWORDS_A                         ; 64              ; Integer                          ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                          ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                          ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                          ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                          ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                          ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                          ;
; WIDTH_B                            ; 1               ; Untyped                          ;
; WIDTHAD_B                          ; 1               ; Untyped                          ;
; NUMWORDS_B                         ; 1               ; Untyped                          ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                          ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                          ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                          ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                          ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                          ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                          ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                          ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                          ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                          ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                          ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                          ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                          ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                          ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                          ;
; BYTE_SIZE                          ; 8               ; Untyped                          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                          ;
; INIT_FILE                          ; zimo.mif        ; Untyped                          ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                          ;
; MAXIMUM_DEPTH                      ; 256             ; Integer                          ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                          ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped                          ;
; CBXI_PARAMETER                     ; altsyncram_d651 ; Untyped                          ;
+------------------------------------+-----------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 15 16:41:59 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off float -c float
Info: Found 1 design units, including 1 entities, in source file hdf.v
    Info: Found entity 1: hdf
Info: Found 1 design units, including 1 entities, in source file saomiao.v
    Info: Found entity 1: saomiao
Info: Found 1 design units, including 1 entities, in source file shj.v
    Info: Found entity 1: shj
Info: Found 1 design units, including 1 entities, in source file float.bdf
    Info: Found entity 1: float
Info: Elaborating entity "float" for the top level hierarchy
Warning: Using design file zimo.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: zimo
Info: Elaborating entity "zimo" for hierarchy "zimo:inst4"
Info: Found 1 design units, including 1 entities, in source file d:/quartus2_setup/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "zimo:inst4|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "zimo:inst4|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_d651.tdf
    Info: Found entity 1: altsyncram_d651
Info: Elaborating entity "altsyncram_d651" for hierarchy "zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated"
Info: Elaborating entity "hdf" for hierarchy "hdf:inst1"
Info: Elaborating entity "saomiao" for hierarchy "saomiao:inst"
Warning (10230): Verilog HDL assignment warning at saomiao.v(8): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "shj" for hierarchy "shj:inst7"
Warning (10230): Verilog HDL assignment warning at shj.v(14): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at shj.v(16): truncated value with size 32 to match size of target (6)
Info: Implemented 58 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 20 output pins
    Info: Implemented 17 logic cells
    Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Thu Nov 15 16:42:00 2007
    Info: Elapsed time: 00:00:02