shj.v

该文档是基于QUARTUS2_6.0的Verilog试验例程

module shj(clk2,clr,stop,control_1,data2);
input clk2,clr,stop;
input control_1;
output[5:0] data2;
reg[5:0] data2;

always @(posedge clk2)
begin
 if (!clr)
   begin
   if(!stop)
     begin 
      if(!control_1)   
        data2<=data2+1;
      else
        data2<=data2-1;
     end   
    else
      data2<=data2;
   end
 else
  data2<=0;
end
endmodule