paobiao.map.qmsg

该文档是基于QUARTUS2_6.0的Verilog试验例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 02 15:07:37 2007 " "Info: Processing started: Sun Dec 02 15:07:37 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off paobiao -c paobiao " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off paobiao -c paobiao" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "second.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file second.v" { { "Info" "ISGN_ENTITY_NAME" "1 second " "Info: Found entity 1: second" {  } { { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "minute.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file minute.v" { { "Info" "ISGN_ENTITY_NAME" "1 minute " "Info: Found entity 1: minute" {  } { { "minute.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/minute.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "select.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file select.v" { { "Info" "ISGN_ENTITY_NAME" "1 select " "Info: Found entity 1: select" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/select.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "saomiao.v(20) " "Warning (10273): Verilog HDL warning at saomiao.v(20): extended using \"x\" or \"z\"" {  } { { "saomiao.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/saomiao.v" 20 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "saomiao.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file saomiao.v" { { "Info" "ISGN_ENTITY_NAME" "1 saomiao " "Info: Found entity 1: saomiao" {  } { { "saomiao.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/saomiao.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yima.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file yima.v" { { "Info" "ISGN_ENTITY_NAME" "1 yima " "Info: Found entity 1: yima" {  } { { "yima.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/yima.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "paobiao.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file paobiao.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 paobiao " "Info: Found entity 1: paobiao" {  } { { "paobiao.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "paobiao " "Info: Elaborating entity \"paobiao\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "yima yima:inst4 " "Info: Elaborating entity \"yima\" for hierarchy \"yima:inst4\"" {  } { { "paobiao.bdf" "inst4" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 0 536 664 96 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "select select:inst5 " "Info: Elaborating entity \"select\" for hierarchy \"select:inst5\"" {  } { { "paobiao.bdf" "inst5" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 0 328 512 128 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "sl_1 select.v(10) " "Warning (10235): Verilog HDL Always Construct warning at select.v(10): variable \"sl_1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/select.v" 10 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "sh_1 select.v(11) " "Warning (10235): Verilog HDL Always Construct warning at select.v(11): variable \"sh_1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/select.v" 11 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "msl_1 select.v(12) " "Warning (10235): Verilog HDL Always Construct warning at select.v(12): variable \"msl_1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/select.v" 12 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "msh_1 select.v(13) " "Warning (10235): Verilog HDL Always Construct warning at select.v(13): variable \"msh_1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/select.v" 13 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "select.v(9) " "Info (10264): Verilog HDL Case Statement information at select.v(9): all case item expressions in this case statement are onehot" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/select.v" 9 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "minute minute:inst " "Info: Elaborating entity \"minute\" for hierarchy \"minute:inst\"" {  } { { "paobiao.bdf" "inst" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 144 136 248 240 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 minute.v(17) " "Warning (10230): Verilog HDL assignment warning at minute.v(17): truncated value with size 32 to match size of target (4)" {  } { { "minute.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/minute.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 minute.v(19) " "Warning (10230): Verilog HDL assignment warning at minute.v(19): truncated value with size 32 to match size of target (4)" {  } { { "minute.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/minute.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "second second:inst2 " "Info: Elaborating entity \"second\" for hierarchy \"second:inst2\"" {  } { { "paobiao.bdf" "inst2" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 0 96 216 96 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 31 second.v(16) " "Warning (10230): Verilog HDL assignment warning at second.v(16): truncated value with size 32 to match size of target (31)" {  } { { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 second.v(37) " "Warning (10230): Verilog HDL assignment warning at second.v(37): truncated value with size 32 to match size of target (4)" {  } { { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 second.v(42) " "Warning (10230): Verilog HDL assignment warning at second.v(42): truncated value with size 32 to match size of target (4)" {  } { { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "saomiao saomiao:inst1 " "Info: Elaborating entity \"saomiao\" for hierarchy \"saomiao:inst1\"" {  } { { "paobiao.bdf" "inst1" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 296 136 232 392 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 saomiao.v(10) " "Warning (10230): Verilog HDL assignment warning at saomiao.v(10): truncated value with size 32 to match size of target (16)" {  } { { "saomiao.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/saomiao.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "143 " "Info: Implemented 143 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "129 " "Info: Implemented 129 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 02 15:07:38 2007 " "Info: Processing ended: Sun Dec 02 15:07:38 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.map.smsg " "Info: Generated suppressed messages file F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}