paobiao.fit.qmsg

该文档是基于QUARTUS2_6.0的Verilog试验例程

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.089 ns register register " "Info: Estimated most critical path is register to register delay of 5.089 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second:inst2\|rr\[2\] 1 REG LAB_X10_Y6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y6; Fanout = 4; REG Node = 'second:inst2\|rr\[2\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { second:inst2|rr[2] } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.362 ns) + CELL(0.114 ns) 1.476 ns second:inst2\|Equal0~348 2 COMB LAB_X9_Y5 1 " "Info: 2: + IC(1.362 ns) + CELL(0.114 ns) = 1.476 ns; Loc. = LAB_X9_Y5; Fanout = 1; COMB Node = 'second:inst2\|Equal0~348'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.476 ns" { second:inst2|rr[2] second:inst2|Equal0~348 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.810 ns) + CELL(0.590 ns) 2.876 ns second:inst2\|Equal0~349 3 COMB LAB_X10_Y6 1 " "Info: 3: + IC(0.810 ns) + CELL(0.590 ns) = 2.876 ns; Loc. = LAB_X10_Y6; Fanout = 1; COMB Node = 'second:inst2\|Equal0~349'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.400 ns" { second:inst2|Equal0~348 second:inst2|Equal0~349 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.114 ns) 3.530 ns second:inst2\|Equal0~350 4 COMB LAB_X10_Y6 9 " "Info: 4: + IC(0.540 ns) + CELL(0.114 ns) = 3.530 ns; Loc. = LAB_X10_Y6; Fanout = 9; COMB Node = 'second:inst2\|Equal0~350'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.654 ns" { second:inst2|Equal0~349 second:inst2|Equal0~350 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.309 ns) 5.089 ns second:inst2\|clk_1 5 REG LAB_X9_Y4 10 " "Info: 5: + IC(1.250 ns) + CELL(0.309 ns) = 5.089 ns; Loc. = LAB_X9_Y4; Fanout = 10; REG Node = 'second:inst2\|clk_1'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.559 ns" { second:inst2|Equal0~350 second:inst2|clk_1 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.127 ns ( 22.15 % ) " "Info: Total cell delay = 1.127 ns ( 22.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.962 ns ( 77.85 % ) " "Info: Total interconnect delay = 3.962 ns ( 77.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.089 ns" { second:inst2|rr[2] second:inst2|Equal0~348 second:inst2|Equal0~349 second:inst2|Equal0~350 second:inst2|clk_1 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 02 15:07:41 2007 " "Info: Processing ended: Sun Dec 02 15:07:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.fit.smsg " "Info: Generated suppressed messages file F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}