paobiao.tan.qmsg

该文档是基于QUARTUS2_6.0的Verilog试验例程

{ "Info" "ITDB_TH_RESULT" "second:inst2\|sl\[0\] clr clk 0.721 ns register " "Info: th for register \"second:inst2\|sl\[0\]\" (data pin = \"clr\", clock pin = \"clk\") is 0.721 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.931 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 42; CLK Node = 'clk'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "paobiao.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 8 -104 64 24 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns second:inst2\|clk_1 2 REG LC_X9_Y4_N1 10 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X9_Y4_N1; Fanout = 10; REG Node = 'second:inst2\|clk_1'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk second:inst2|clk_1 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.266 ns) + CELL(0.711 ns) 7.931 ns second:inst2\|sl\[0\] 3 REG LC_X24_Y3_N4 6 " "Info: 3: + IC(4.266 ns) + CELL(0.711 ns) = 7.931 ns; Loc. = LC_X24_Y3_N4; Fanout = 6; REG Node = 'second:inst2\|sl\[0\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "4.977 ns" { second:inst2|clk_1 second:inst2|sl[0] } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.28 % ) " "Info: Total cell delay = 3.115 ns ( 39.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.816 ns ( 60.72 % ) " "Info: Total interconnect delay = 4.816 ns ( 60.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.931 ns" { clk second:inst2|clk_1 second:inst2|sl[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.931 ns" { clk clk~out0 second:inst2|clk_1 second:inst2|sl[0] } { 0.000ns 0.000ns 0.550ns 4.266ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 51 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.225 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.225 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clr 1 PIN PIN_67 19 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_67; Fanout = 19; PIN Node = 'clr'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "paobiao.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 40 -104 64 56 "clr" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.441 ns) + CELL(0.309 ns) 7.225 ns second:inst2\|sl\[0\] 2 REG LC_X24_Y3_N4 6 " "Info: 2: + IC(5.441 ns) + CELL(0.309 ns) = 7.225 ns; Loc. = LC_X24_Y3_N4; Fanout = 6; REG Node = 'second:inst2\|sl\[0\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.750 ns" { clr second:inst2|sl[0] } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns ( 24.69 % ) " "Info: Total cell delay = 1.784 ns ( 24.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.441 ns ( 75.31 % ) " "Info: Total interconnect delay = 5.441 ns ( 75.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.225 ns" { clr second:inst2|sl[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.225 ns" { clr clr~out0 second:inst2|sl[0] } { 0.000ns 0.000ns 5.441ns } { 0.000ns 1.475ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.931 ns" { clk second:inst2|clk_1 second:inst2|sl[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.931 ns" { clk clk~out0 second:inst2|clk_1 second:inst2|sl[0] } { 0.000ns 0.000ns 0.550ns 4.266ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.225 ns" { clr second:inst2|sl[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.225 ns" { clr clr~out0 second:inst2|sl[0] } { 0.000ns 0.000ns 5.441ns } { 0.000ns 1.475ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 02 15:07:46 2007 " "Info: Processing ended: Sun Dec 02 15:07:46 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}