📄 paobiao.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "second:inst2\|cn " "Info: Detected ripple clock \"second:inst2\|cn\" as buffer" { } { { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 4 -1 0 } } { "d:/quartus2_setup/win/Assignment Editor.qase" "" { Assignment "d:/quartus2_setup/win/Assignment Editor.qase" 1 { { 0 "second:inst2\|cn" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "second:inst2\|clk_1 " "Info: Detected ripple clock \"second:inst2\|clk_1\" as buffer" { } { { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 6 -1 0 } } { "d:/quartus2_setup/win/Assignment Editor.qase" "" { Assignment "d:/quartus2_setup/win/Assignment Editor.qase" 1 { { 0 "second:inst2\|clk_1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register second:inst2\|rr\[2\] register second:inst2\|clk_1 175.07 MHz 5.712 ns Internal " "Info: Clock \"clk\" has Internal fmax of 175.07 MHz between source register \"second:inst2\|rr\[2\]\" and destination register \"second:inst2\|clk_1\" (period= 5.712 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.441 ns + Longest register register " "Info: + Longest register to register delay is 5.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second:inst2\|rr\[2\] 1 REG LC_X10_Y6_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y6_N1; Fanout = 4; REG Node = 'second:inst2\|rr\[2\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { second:inst2|rr[2] } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.114 ns) 1.379 ns second:inst2\|Equal0~348 2 COMB LC_X9_Y5_N2 1 " "Info: 2: + IC(1.265 ns) + CELL(0.114 ns) = 1.379 ns; Loc. = LC_X9_Y5_N2; Fanout = 1; COMB Node = 'second:inst2\|Equal0~348'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.379 ns" { second:inst2|rr[2] second:inst2|Equal0~348 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.442 ns) 3.036 ns second:inst2\|Equal0~349 3 COMB LC_X10_Y6_N2 1 " "Info: 3: + IC(1.215 ns) + CELL(0.442 ns) = 3.036 ns; Loc. = LC_X10_Y6_N2; Fanout = 1; COMB Node = 'second:inst2\|Equal0~349'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.657 ns" { second:inst2|Equal0~348 second:inst2|Equal0~349 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.292 ns) 3.770 ns second:inst2\|Equal0~350 4 COMB LC_X10_Y6_N0 9 " "Info: 4: + IC(0.442 ns) + CELL(0.292 ns) = 3.770 ns; Loc. = LC_X10_Y6_N0; Fanout = 9; COMB Node = 'second:inst2\|Equal0~350'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.734 ns" { second:inst2|Equal0~349 second:inst2|Equal0~350 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.362 ns) + CELL(0.309 ns) 5.441 ns second:inst2\|clk_1 5 REG LC_X9_Y4_N1 10 " "Info: 5: + IC(1.362 ns) + CELL(0.309 ns) = 5.441 ns; Loc. = LC_X9_Y4_N1; Fanout = 10; REG Node = 'second:inst2\|clk_1'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.671 ns" { second:inst2|Equal0~350 second:inst2|clk_1 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.157 ns ( 21.26 % ) " "Info: Total cell delay = 1.157 ns ( 21.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.284 ns ( 78.74 % ) " "Info: Total interconnect delay = 4.284 ns ( 78.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.441 ns" { second:inst2|rr[2] second:inst2|Equal0~348 second:inst2|Equal0~349 second:inst2|Equal0~350 second:inst2|clk_1 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "5.441 ns" { second:inst2|rr[2] second:inst2|Equal0~348 second:inst2|Equal0~349 second:inst2|Equal0~350 second:inst2|clk_1 } { 0.000ns 1.265ns 1.215ns 0.442ns 1.362ns } { 0.000ns 0.114ns 0.442ns 0.292ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.010 ns - Smallest " "Info: - Smallest clock skew is -0.010 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 42; CLK Node = 'clk'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "paobiao.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 8 -104 64 24 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns second:inst2\|clk_1 2 REG LC_X9_Y4_N1 10 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y4_N1; Fanout = 10; REG Node = 'second:inst2\|clk_1'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.261 ns" { clk second:inst2|clk_1 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.730 ns" { clk second:inst2|clk_1 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 second:inst2|clk_1 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 42; CLK Node = 'clk'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "paobiao.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 8 -104 64 24 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns second:inst2\|rr\[2\] 2 REG LC_X10_Y6_N1 4 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X10_Y6_N1; Fanout = 4; REG Node = 'second:inst2\|rr\[2\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.271 ns" { clk second:inst2|rr[2] } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk second:inst2|rr[2] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 second:inst2|rr[2] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.730 ns" { clk second:inst2|clk_1 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 second:inst2|clk_1 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk second:inst2|rr[2] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 second:inst2|rr[2] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 6 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.441 ns" { second:inst2|rr[2] second:inst2|Equal0~348 second:inst2|Equal0~349 second:inst2|Equal0~350 second:inst2|clk_1 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "5.441 ns" { second:inst2|rr[2] second:inst2|Equal0~348 second:inst2|Equal0~349 second:inst2|Equal0~350 second:inst2|clk_1 } { 0.000ns 1.265ns 1.215ns 0.442ns 1.362ns } { 0.000ns 0.114ns 0.442ns 0.292ns 0.309ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.730 ns" { clk second:inst2|clk_1 } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 second:inst2|clk_1 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk second:inst2|rr[2] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 second:inst2|rr[2] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "second:inst2\|sl\[3\] pause clk 1.378 ns register " "Info: tsu for register \"second:inst2\|sl\[3\]\" (data pin = \"pause\", clock pin = \"clk\") is 1.378 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.272 ns + Longest pin register " "Info: + Longest pin to register delay is 9.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns pause 1 PIN PIN_68 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_68; Fanout = 4; PIN Node = 'pause'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { pause } "NODE_NAME" } } { "paobiao.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 72 -104 64 88 "pause" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.425 ns) + CELL(0.292 ns) 7.192 ns second:inst2\|sl\[3\]~323 2 COMB LC_X24_Y3_N2 4 " "Info: 2: + IC(5.425 ns) + CELL(0.292 ns) = 7.192 ns; Loc. = LC_X24_Y3_N2; Fanout = 4; COMB Node = 'second:inst2\|sl\[3\]~323'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.717 ns" { pause second:inst2|sl[3]~323 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 51 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(0.867 ns) 9.272 ns second:inst2\|sl\[3\] 3 REG LC_X24_Y2_N5 3 " "Info: 3: + IC(1.213 ns) + CELL(0.867 ns) = 9.272 ns; Loc. = LC_X24_Y2_N5; Fanout = 3; REG Node = 'second:inst2\|sl\[3\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.080 ns" { second:inst2|sl[3]~323 second:inst2|sl[3] } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 51 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.634 ns ( 28.41 % ) " "Info: Total cell delay = 2.634 ns ( 28.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.638 ns ( 71.59 % ) " "Info: Total interconnect delay = 6.638 ns ( 71.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "9.272 ns" { pause second:inst2|sl[3]~323 second:inst2|sl[3] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "9.272 ns" { pause pause~out0 second:inst2|sl[3]~323 second:inst2|sl[3] } { 0.000ns 0.000ns 5.425ns 1.213ns } { 0.000ns 1.475ns 0.292ns 0.867ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 51 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.931 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 42; CLK Node = 'clk'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "paobiao.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 8 -104 64 24 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns second:inst2\|clk_1 2 REG LC_X9_Y4_N1 10 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X9_Y4_N1; Fanout = 10; REG Node = 'second:inst2\|clk_1'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk second:inst2|clk_1 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.266 ns) + CELL(0.711 ns) 7.931 ns second:inst2\|sl\[3\] 3 REG LC_X24_Y2_N5 3 " "Info: 3: + IC(4.266 ns) + CELL(0.711 ns) = 7.931 ns; Loc. = LC_X24_Y2_N5; Fanout = 3; REG Node = 'second:inst2\|sl\[3\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "4.977 ns" { second:inst2|clk_1 second:inst2|sl[3] } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 51 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.28 % ) " "Info: Total cell delay = 3.115 ns ( 39.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.816 ns ( 60.72 % ) " "Info: Total interconnect delay = 4.816 ns ( 60.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.931 ns" { clk second:inst2|clk_1 second:inst2|sl[3] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.931 ns" { clk clk~out0 second:inst2|clk_1 second:inst2|sl[3] } { 0.000ns 0.000ns 0.550ns 4.266ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "9.272 ns" { pause second:inst2|sl[3]~323 second:inst2|sl[3] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "9.272 ns" { pause pause~out0 second:inst2|sl[3]~323 second:inst2|sl[3] } { 0.000ns 0.000ns 5.425ns 1.213ns } { 0.000ns 1.475ns 0.292ns 0.867ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.931 ns" { clk second:inst2|clk_1 second:inst2|sl[3] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.931 ns" { clk clk~out0 second:inst2|clk_1 second:inst2|sl[3] } { 0.000ns 0.000ns 0.550ns 4.266ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q_out\[0\] minute:inst\|msl\[0\] 21.926 ns register " "Info: tco from clock \"clk\" to destination pin \"q_out\[0\]\" through register \"minute:inst\|msl\[0\]\" is 21.926 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.291 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 13.291 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 42; CLK Node = 'clk'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "paobiao.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 8 -104 64 24 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns second:inst2\|clk_1 2 REG LC_X9_Y4_N1 10 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X9_Y4_N1; Fanout = 10; REG Node = 'second:inst2\|clk_1'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk second:inst2|clk_1 } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.266 ns) + CELL(0.935 ns) 8.155 ns second:inst2\|cn 3 REG LC_X24_Y3_N8 9 " "Info: 3: + IC(4.266 ns) + CELL(0.935 ns) = 8.155 ns; Loc. = LC_X24_Y3_N8; Fanout = 9; REG Node = 'second:inst2\|cn'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.201 ns" { second:inst2|clk_1 second:inst2|cn } "NODE_NAME" } } { "second.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/second.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.425 ns) + CELL(0.711 ns) 13.291 ns minute:inst\|msl\[0\] 4 REG LC_X25_Y2_N2 6 " "Info: 4: + IC(4.425 ns) + CELL(0.711 ns) = 13.291 ns; Loc. = LC_X25_Y2_N2; Fanout = 6; REG Node = 'minute:inst\|msl\[0\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.136 ns" { second:inst2|cn minute:inst|msl[0] } "NODE_NAME" } } { "minute.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/minute.v" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 30.47 % ) " "Info: Total cell delay = 4.050 ns ( 30.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.241 ns ( 69.53 % ) " "Info: Total interconnect delay = 9.241 ns ( 69.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "13.291 ns" { clk second:inst2|clk_1 second:inst2|cn minute:inst|msl[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "13.291 ns" { clk clk~out0 second:inst2|clk_1 second:inst2|cn minute:inst|msl[0] } { 0.000ns 0.000ns 0.550ns 4.266ns 4.425ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "minute.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/minute.v" 8 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.411 ns + Longest register pin " "Info: + Longest register to pin delay is 8.411 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute:inst\|msl\[0\] 1 REG LC_X25_Y2_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y2_N2; Fanout = 6; REG Node = 'minute:inst\|msl\[0\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { minute:inst|msl[0] } "NODE_NAME" } } { "minute.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/minute.v" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.617 ns) + CELL(0.292 ns) 1.909 ns select:inst5\|Selector3~45 2 COMB LC_X24_Y3_N5 1 " "Info: 2: + IC(1.617 ns) + CELL(0.292 ns) = 1.909 ns; Loc. = LC_X24_Y3_N5; Fanout = 1; COMB Node = 'select:inst5\|Selector3~45'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.909 ns" { minute:inst|msl[0] select:inst5|Selector3~45 } "NODE_NAME" } } { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/select.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.205 ns select:inst5\|Selector3~46 3 COMB LC_X24_Y3_N6 7 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.205 ns; Loc. = LC_X24_Y3_N6; Fanout = 7; COMB Node = 'select:inst5\|Selector3~46'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.296 ns" { select:inst5|Selector3~45 select:inst5|Selector3~46 } "NODE_NAME" } } { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/select.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.114 ns) 3.696 ns yima:inst4\|out~49 4 COMB LC_X25_Y4_N6 1 " "Info: 4: + IC(1.377 ns) + CELL(0.114 ns) = 3.696 ns; Loc. = LC_X25_Y4_N6; Fanout = 1; COMB Node = 'yima:inst4\|out~49'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.491 ns" { select:inst5|Selector3~46 yima:inst4|out~49 } "NODE_NAME" } } { "yima.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/yima.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.591 ns) + CELL(2.124 ns) 8.411 ns q_out\[0\] 5 PIN PIN_108 0 " "Info: 5: + IC(2.591 ns) + CELL(2.124 ns) = 8.411 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'q_out\[0\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "4.715 ns" { yima:inst4|out~49 q_out[0] } "NODE_NAME" } } { "paobiao.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/paobiao/paobiao.bdf" { { 24 688 864 40 "q_out\[6..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.644 ns ( 31.44 % ) " "Info: Total cell delay = 2.644 ns ( 31.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.767 ns ( 68.56 % ) " "Info: Total interconnect delay = 5.767 ns ( 68.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.411 ns" { minute:inst|msl[0] select:inst5|Selector3~45 select:inst5|Selector3~46 yima:inst4|out~49 q_out[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.411 ns" { minute:inst|msl[0] select:inst5|Selector3~45 select:inst5|Selector3~46 yima:inst4|out~49 q_out[0] } { 0.000ns 1.617ns 0.182ns 1.377ns 2.591ns } { 0.000ns 0.292ns 0.114ns 0.114ns 2.124ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "13.291 ns" { clk second:inst2|clk_1 second:inst2|cn minute:inst|msl[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "13.291 ns" { clk clk~out0 second:inst2|clk_1 second:inst2|cn minute:inst|msl[0] } { 0.000ns 0.000ns 0.550ns 4.266ns 4.425ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.411 ns" { minute:inst|msl[0] select:inst5|Selector3~45 select:inst5|Selector3~46 yima:inst4|out~49 q_out[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.411 ns" { minute:inst|msl[0] select:inst5|Selector3~45 select:inst5|Selector3~46 yima:inst4|out~49 q_out[0] } { 0.000ns 1.617ns 0.182ns 1.377ns 2.591ns } { 0.000ns 0.292ns 0.114ns 0.114ns 2.124ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -