minute.v

该文档是基于QUARTUS2_6.0的Verilog试验例程

module minute(cn,clr,msl,msh);
input cn,clr;
output[3:0] msl,msh;
reg[3:0] msl,msh;

always @(posedge cn or negedge clr)
begin 
 if(!clr)
   begin
    msl<=0;
    msh<=0;
   end
 else if(msl==5)
   begin
    msl<=0;
    if(msh==9)   msh<=0;
    else         msh<=msh+1;
   end
 else   msl<=msl+1;  
end
endmodule