second.v

该文档是基于QUARTUS2_6.0的Verilog试验例程

module second(clk,clr,pause,sl,sh,cn);
input clk,clr,pause;
output[3:0] sl,sh;
output cn;
reg[3:0] sl,sh;
reg cn,clk_1;
reg[30:0] rr;

always @(posedge clk)
begin 
 if(rr==1000000)  
  begin
   rr=0;
   clk_1=~clk_1;
  end
 else  rr=rr+1;
end  
 
always @(posedge clk_1 )
begin
 if(!clr)            //低电平清零
   begin
    sl<=0;
    sh<=0;
    cn<=0;
   end
 else if(!pause)
   begin
     if(sl==9)
       begin
        sl<=0;
        if(sh==9)
          begin
           sh<=0;
           cn<=1;
          end
        else  sh<=sh+1;
       end
     else 
      begin
       cn<=0;
       sl<=sl+1;
      end
   end
 else  if(!pause)     //低电平暂停
   begin 
    sl<=sl;
    sh<=sh;
    cn<=cn;
   end
 end
endmodule