zz.map.qmsg

该文档是基于QUARTUS2_6.0的Verilog试验例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 14 08:40:39 2007 " "Info: Processing started: Wed Nov 14 08:40:39 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off zz -c zz " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off zz -c zz" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shuzizhong.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file shuzizhong.v" { { "Info" "ISGN_ENTITY_NAME" "1 shuzizhong " "Info: Found entity 1: shuzizhong" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "shuzizhong " "Info: Elaborating entity \"shuzizhong\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 31 shuzizhong.v(15) " "Warning (10230): Verilog HDL assignment warning at shuzizhong.v(15): truncated value with size 32 to match size of target (31)" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 shuzizhong.v(24) " "Warning (10230): Verilog HDL assignment warning at shuzizhong.v(24): truncated value with size 32 to match size of target (24)" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 shuzizhong.v(28) " "Warning (10230): Verilog HDL assignment warning at shuzizhong.v(28): truncated value with size 32 to match size of target (4)" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 shuzizhong.v(32) " "Warning (10230): Verilog HDL assignment warning at shuzizhong.v(32): truncated value with size 32 to match size of target (4)" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 shuzizhong.v(36) " "Warning (10230): Verilog HDL assignment warning at shuzizhong.v(36): truncated value with size 32 to match size of target (4)" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 36 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 shuzizhong.v(40) " "Warning (10230): Verilog HDL assignment warning at shuzizhong.v(40): truncated value with size 32 to match size of target (8)" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 shuzizhong.v(48) " "Warning (10230): Verilog HDL assignment warning at shuzizhong.v(48): truncated value with size 32 to match size of target (4)" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min shuzizhong.v(70) " "Warning (10235): Verilog HDL Always Construct warning at shuzizhong.v(70): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 70 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min shuzizhong.v(71) " "Warning (10235): Verilog HDL Always Construct warning at shuzizhong.v(71): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 71 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min shuzizhong.v(72) " "Warning (10235): Verilog HDL Always Construct warning at shuzizhong.v(72): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 72 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min shuzizhong.v(73) " "Warning (10235): Verilog HDL Always Construct warning at shuzizhong.v(73): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 73 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min shuzizhong.v(74) " "Warning (10235): Verilog HDL Always Construct warning at shuzizhong.v(74): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 74 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min shuzizhong.v(75) " "Warning (10235): Verilog HDL Always Construct warning at shuzizhong.v(75): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 75 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "191 " "Info: Implemented 191 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "177 " "Info: Implemented 177 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 14 08:40:41 2007 " "Info: Processing ended: Wed Nov 14 08:40:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}