zz.tan.qmsg

该文档是基于QUARTUS2_6.0的Verilog试验例程

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register min\[7\] register min\[19\] 110.17 MHz 9.077 ns Internal " "Info: Clock \"clk\" has Internal fmax of 110.17 MHz between source register \"min\[7\]\" and destination register \"min\[19\]\" (period= 9.077 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.816 ns + Longest register register " "Info: + Longest register to register delay is 8.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns min\[7\] 1 REG LC_X22_Y11_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y11_N1; Fanout = 4; REG Node = 'min\[7\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { min[7] } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.259 ns) + CELL(0.423 ns) 1.682 ns Add1~409 2 COMB LC_X23_Y10_N0 2 " "Info: 2: + IC(1.259 ns) + CELL(0.423 ns) = 1.682 ns; Loc. = LC_X23_Y10_N0; Fanout = 2; COMB Node = 'Add1~409'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.682 ns" { min[7] Add1~409 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.760 ns Add1~411 3 COMB LC_X23_Y10_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.760 ns; Loc. = LC_X23_Y10_N1; Fanout = 2; COMB Node = 'Add1~411'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { Add1~409 Add1~411 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.838 ns Add1~413 4 COMB LC_X23_Y10_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.838 ns; Loc. = LC_X23_Y10_N2; Fanout = 2; COMB Node = 'Add1~413'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { Add1~411 Add1~413 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.916 ns Add1~415 5 COMB LC_X23_Y10_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.916 ns; Loc. = LC_X23_Y10_N3; Fanout = 2; COMB Node = 'Add1~415'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { Add1~413 Add1~415 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.094 ns Add1~417 6 COMB LC_X23_Y10_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 2.094 ns; Loc. = LC_X23_Y10_N4; Fanout = 6; COMB Node = 'Add1~417'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.178 ns" { Add1~415 Add1~417 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.715 ns Add1~400 7 COMB LC_X23_Y10_N9 4 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.715 ns; Loc. = LC_X23_Y10_N9; Fanout = 4; COMB Node = 'Add1~400'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.621 ns" { Add1~417 Add1~400 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(0.432 ns) 4.324 ns Add5~118COUT1_134 8 COMB LC_X24_Y9_N0 2 " "Info: 8: + IC(1.177 ns) + CELL(0.432 ns) = 4.324 ns; Loc. = LC_X24_Y9_N0; Fanout = 2; COMB Node = 'Add5~118COUT1_134'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.609 ns" { Add1~400 Add5~118COUT1_134 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 4.932 ns Add5~121 9 COMB LC_X24_Y9_N1 3 " "Info: 9: + IC(0.000 ns) + CELL(0.608 ns) = 4.932 ns; Loc. = LC_X24_Y9_N1; Fanout = 3; COMB Node = 'Add5~121'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.608 ns" { Add5~118COUT1_134 Add5~121 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.590 ns) 5.947 ns always1~54 10 COMB LC_X24_Y9_N9 1 " "Info: 10: + IC(0.425 ns) + CELL(0.590 ns) = 5.947 ns; Loc. = LC_X24_Y9_N9; Fanout = 1; COMB Node = 'always1~54'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.015 ns" { Add5~121 always1~54 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.684 ns) + CELL(0.442 ns) 7.073 ns always1~0 11 COMB LC_X25_Y9_N7 2 " "Info: 11: + IC(0.684 ns) + CELL(0.442 ns) = 7.073 ns; Loc. = LC_X25_Y9_N7; Fanout = 2; COMB Node = 'always1~0'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.126 ns" { always1~54 always1~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 7.369 ns min\[19\]~2540 12 COMB LC_X25_Y9_N8 4 " "Info: 12: + IC(0.182 ns) + CELL(0.114 ns) = 7.369 ns; Loc. = LC_X25_Y9_N8; Fanout = 4; COMB Node = 'min\[19\]~2540'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.296 ns" { always1~0 min[19]~2540 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.138 ns) + CELL(0.309 ns) 8.816 ns min\[19\] 13 REG LC_X23_Y9_N9 4 " "Info: 13: + IC(1.138 ns) + CELL(0.309 ns) = 8.816 ns; Loc. = LC_X23_Y9_N9; Fanout = 4; REG Node = 'min\[19\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.447 ns" { min[19]~2540 min[19] } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.951 ns ( 44.82 % ) " "Info: Total cell delay = 3.951 ns ( 44.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.865 ns ( 55.18 % ) " "Info: Total interconnect delay = 4.865 ns ( 55.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.816 ns" { min[7] Add1~409 Add1~411 Add1~413 Add1~415 Add1~417 Add1~400 Add5~118COUT1_134 Add5~121 always1~54 always1~0 min[19]~2540 min[19] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.816 ns" { min[7] Add1~409 Add1~411 Add1~413 Add1~415 Add1~417 Add1~400 Add5~118COUT1_134 Add5~121 always1~54 always1~0 min[19]~2540 min[19] } { 0.000ns 1.259ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.177ns 0.000ns 0.425ns 0.684ns 0.182ns 1.138ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.432ns 0.608ns 0.590ns 0.442ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.055 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.055 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 32; CLK Node = 'clk'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns sec 2 REG LC_X15_Y6_N4 25 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X15_Y6_N4; Fanout = 25; REG Node = 'sec'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.537 ns" { clk sec } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.338 ns) + CELL(0.711 ns) 8.055 ns min\[19\] 3 REG LC_X23_Y9_N9 4 " "Info: 3: + IC(4.338 ns) + CELL(0.711 ns) = 8.055 ns; Loc. = LC_X23_Y9_N9; Fanout = 4; REG Node = 'min\[19\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.049 ns" { sec min[19] } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.67 % ) " "Info: Total cell delay = 3.115 ns ( 38.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.940 ns ( 61.33 % ) " "Info: Total interconnect delay = 4.940 ns ( 61.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.055 ns" { clk sec min[19] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.055 ns" { clk clk~out0 sec min[19] } { 0.000ns 0.000ns 0.602ns 4.338ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.055 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.055 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 32; CLK Node = 'clk'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns sec 2 REG LC_X15_Y6_N4 25 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X15_Y6_N4; Fanout = 25; REG Node = 'sec'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.537 ns" { clk sec } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.338 ns) + CELL(0.711 ns) 8.055 ns min\[7\] 3 REG LC_X22_Y11_N1 4 " "Info: 3: + IC(4.338 ns) + CELL(0.711 ns) = 8.055 ns; Loc. = LC_X22_Y11_N1; Fanout = 4; REG Node = 'min\[7\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.049 ns" { sec min[7] } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.67 % ) " "Info: Total cell delay = 3.115 ns ( 38.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.940 ns ( 61.33 % ) " "Info: Total interconnect delay = 4.940 ns ( 61.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.055 ns" { clk sec min[7] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.055 ns" { clk clk~out0 sec min[7] } { 0.000ns 0.000ns 0.602ns 4.338ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.055 ns" { clk sec min[19] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.055 ns" { clk clk~out0 sec min[19] } { 0.000ns 0.000ns 0.602ns 4.338ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.055 ns" { clk sec min[7] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.055 ns" { clk clk~out0 sec min[7] } { 0.000ns 0.000ns 0.602ns 4.338ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.816 ns" { min[7] Add1~409 Add1~411 Add1~413 Add1~415 Add1~417 Add1~400 Add5~118COUT1_134 Add5~121 always1~54 always1~0 min[19]~2540 min[19] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.816 ns" { min[7] Add1~409 Add1~411 Add1~413 Add1~415 Add1~417 Add1~400 Add5~118COUT1_134 Add5~121 always1~54 always1~0 min[19]~2540 min[19] } { 0.000ns 1.259ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.177ns 0.000ns 0.425ns 0.684ns 0.182ns 1.138ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.432ns 0.608ns 0.590ns 0.442ns 0.114ns 0.309ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.055 ns" { clk sec min[19] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.055 ns" { clk clk~out0 sec min[19] } { 0.000ns 0.000ns 0.602ns 4.338ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.055 ns" { clk sec min[7] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.055 ns" { clk clk~out0 sec min[7] } { 0.000ns 0.000ns 0.602ns 4.338ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk duan\[6\] min\[3\] 18.055 ns register " "Info: tco from clock \"clk\" to destination pin \"duan\[6\]\" through register \"min\[3\]\" is 18.055 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.055 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.055 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 32; CLK Node = 'clk'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns sec 2 REG LC_X15_Y6_N4 25 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X15_Y6_N4; Fanout = 25; REG Node = 'sec'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.537 ns" { clk sec } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.338 ns) + CELL(0.711 ns) 8.055 ns min\[3\] 3 REG LC_X23_Y11_N1 4 " "Info: 3: + IC(4.338 ns) + CELL(0.711 ns) = 8.055 ns; Loc. = LC_X23_Y11_N1; Fanout = 4; REG Node = 'min\[3\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "5.049 ns" { sec min[3] } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.67 % ) " "Info: Total cell delay = 3.115 ns ( 38.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.940 ns ( 61.33 % ) " "Info: Total interconnect delay = 4.940 ns ( 61.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.055 ns" { clk sec min[3] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.055 ns" { clk clk~out0 sec min[3] } { 0.000ns 0.000ns 0.602ns 4.338ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.776 ns + Longest register pin " "Info: + Longest register to pin delay is 9.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns min\[3\] 1 REG LC_X23_Y11_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y11_N1; Fanout = 4; REG Node = 'min\[3\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { min[3] } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.905 ns) + CELL(0.292 ns) 2.197 ns Selector0~125 2 COMB LC_X23_Y8_N3 1 " "Info: 2: + IC(1.905 ns) + CELL(0.292 ns) = 2.197 ns; Loc. = LC_X23_Y8_N3; Fanout = 1; COMB Node = 'Selector0~125'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.197 ns" { min[3] Selector0~125 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.493 ns Selector0~126 3 COMB LC_X23_Y8_N4 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.493 ns; Loc. = LC_X23_Y8_N4; Fanout = 1; COMB Node = 'Selector0~126'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.296 ns" { Selector0~125 Selector0~126 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.223 ns) + CELL(0.442 ns) 4.158 ns Selector0~128 4 COMB LC_X24_Y10_N6 7 " "Info: 4: + IC(1.223 ns) + CELL(0.442 ns) = 4.158 ns; Loc. = LC_X24_Y10_N6; Fanout = 7; COMB Node = 'Selector0~128'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.665 ns" { Selector0~126 Selector0~128 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.667 ns) + CELL(0.292 ns) 6.117 ns WideOr0~21 5 COMB LC_X26_Y11_N8 1 " "Info: 5: + IC(1.667 ns) + CELL(0.292 ns) = 6.117 ns; Loc. = LC_X26_Y11_N8; Fanout = 1; COMB Node = 'WideOr0~21'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.959 ns" { Selector0~128 WideOr0~21 } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.535 ns) + CELL(2.124 ns) 9.776 ns duan\[6\] 6 PIN PIN_98 0 " "Info: 6: + IC(1.535 ns) + CELL(2.124 ns) = 9.776 ns; Loc. = PIN_98; Fanout = 0; PIN Node = 'duan\[6\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "3.659 ns" { WideOr0~21 duan[6] } "NODE_NAME" } } { "shuzizhong.v" "" { Text "F:/wangbin/例程/新建文件夹/程序/shuzizhong/shuzizhong.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.264 ns ( 33.39 % ) " "Info: Total cell delay = 3.264 ns ( 33.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.512 ns ( 66.61 % ) " "Info: Total interconnect delay = 6.512 ns ( 66.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "9.776 ns" { min[3] Selector0~125 Selector0~126 Selector0~128 WideOr0~21 duan[6] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "9.776 ns" { min[3] Selector0~125 Selector0~126 Selector0~128 WideOr0~21 duan[6] } { 0.000ns 1.905ns 0.182ns 1.223ns 1.667ns 1.535ns } { 0.000ns 0.292ns 0.114ns 0.442ns 0.292ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.055 ns" { clk sec min[3] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.055 ns" { clk clk~out0 sec min[3] } { 0.000ns 0.000ns 0.602ns 4.338ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "9.776 ns" { min[3] Selector0~125 Selector0~126 Selector0~128 WideOr0~21 duan[6] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "9.776 ns" { min[3] Selector0~125 Selector0~126 Selector0~128 WideOr0~21 duan[6] } { 0.000ns 1.905ns 0.182ns 1.223ns 1.667ns 1.535ns } { 0.000ns 0.292ns 0.114ns 0.442ns 0.292ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 14 08:40:49 2007 " "Info: Processing ended: Wed Nov 14 08:40:49 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}