shuzizhong.v

该文档是基于QUARTUS2_6.0的Verilog试验例程

module shuzizhong(clk,duan,wei);
input clk;
output[6:0]duan;
output[5:0]wei;

reg[6:0]duan1;
reg[5:0]wei1;
reg[30:0]count;
reg[23:0]min;
reg sec;
reg[3:0]led;

always @(posedge clk)
 begin 
   count=count+1;
   if(count==10000000) 
    begin
      sec=~sec;
      count=0;
    end 
 end
always @(negedge sec)
 begin
  min=min+1;
  if(min[3:0]==10)
   begin
     min[3:0]=0;
     min[7:4]=min[7:4]+1;
    if(min[7:4]==6)
      begin
       min[7:4]=0; 
       min[11:8]=min[11:8]+1;
       if(min[11:8]==10)
       begin
        min[11:8]=0;
        min[15:12]=min[15:12]+1;
        if(min[15:12]==6)
          begin
            min[15:12]=0; 
            min[23:16]=min[23:16]+1;
           if(min[23:20]==2&&min[19:16]==4)
             begin
              min[23:0]=0;
             end
            else if(min[19:16]==10)
                   begin
                    min[19:16]=0;
                    min[23:20]=min[23:20]+1;
                   end
          end
       end
     end
   end
 end 
always @(count[9:7])
  begin
   case(count[9:7])
    3'b000:wei1=6'b000001;
    3'b001:wei1=6'b000010;
    3'b010:wei1=6'b000100;
    3'b011:wei1=6'b001000;
    3'b100:wei1=6'b010000;
    3'b101:wei1=6'b100000;
   default  wei1=6'b000000;
   endcase
 end  
always @(count[9:7])
  begin
   case(count[9:7])
    3'b000:led=min[3:0];
    3'b001:led=min[7:4];
    3'b010:led=min[11:8];
    3'b011:led=min[15:12];
    3'b100:led=min[19:16];
    3'b101:led=min[23:20];
   default led=4'b0000;
   endcase
 end  
always @(led)
 begin
  case(led)
   4'd0:duan1=7'b0111111;
   4'd1:duan1=7'b0000110;
   4'd2:duan1=7'b1011011;
   4'd3:duan1=7'b1001111;
   4'd4:duan1=7'b1100110;
   4'd5:duan1=7'b1101101;
   4'd6:duan1=7'b1111101;
   4'd7:duan1=7'b0000111;
   4'd8:duan1=7'b1111111;
   4'd9:duan1=7'b1101111;
   default:duan1=7'b0000000;
  endcase
end
assign duan=duan1;
assign wei=wei1;
endmodule