saomiao.v

该文档是基于QUARTUS2_6.0的Verilog试验例程

module saomiao(clk,cel);
input clk;
output[7:0] cel;
reg[7:0] cel;
reg[10:0] clkx;
reg mm;

always @(posedge clk)
begin        
    clkx=clkx+1;
end

always @(clkx[9:7])
begin
  case(clkx[9:7])
    0:cel=8'b00000001;
    1:cel=8'b00000010;
    2:cel=8'b00000100;
    3:cel=8'b00001000;
    4:cel=8'b00010000;
    5:cel=8'b00100000;
    6:cel=8'b01000000;
    7:cel=8'b10000000;
    default:cel=4'bx;
   endcase
end
endmodule