plvji.tan.qmsg

该文档是基于QUARTUS2_6.0的Verilog试验例程

{ "Info" "ITDB_FULL_TCO_RESULT" "clkx duan\[0\] ceping:inst\|data\[21\] 20.337 ns register " "Info: tco from clock \"clkx\" to destination pin \"duan\[0\]\" through register \"ceping:inst\|data\[21\]\" is 20.337 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx source 7.493 ns + Longest register " "Info: + Longest clock path from clock \"clkx\" to source register is 7.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clkx 1 CLK PIN_122 65 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 65; CLK Node = 'clkx'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clkx } "NODE_NAME" } } { "plvji.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.bdf" { { 248 -8 160 264 "clkx" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.307 ns) + CELL(0.711 ns) 7.493 ns ceping:inst\|data\[21\] 2 REG LC_X25_Y7_N0 1 " "Info: 2: + IC(5.307 ns) + CELL(0.711 ns) = 7.493 ns; Loc. = LC_X25_Y7_N0; Fanout = 1; REG Node = 'ceping:inst\|data\[21\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "6.018 ns" { clkx ceping:inst|data[21] } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.17 % ) " "Info: Total cell delay = 2.186 ns ( 29.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.307 ns ( 70.83 % ) " "Info: Total interconnect delay = 5.307 ns ( 70.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.493 ns" { clkx ceping:inst|data[21] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.493 ns" { clkx clkx~out0 ceping:inst|data[21] } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.620 ns + Longest register pin " "Info: + Longest register to pin delay is 12.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ceping:inst\|data\[21\] 1 REG LC_X25_Y7_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y7_N0; Fanout = 1; REG Node = 'ceping:inst\|data\[21\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { ceping:inst|data[21] } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(0.114 ns) 0.628 ns select:inst2\|Selector2~195 2 COMB LC_X25_Y7_N2 1 " "Info: 2: + IC(0.514 ns) + CELL(0.114 ns) = 0.628 ns; Loc. = LC_X25_Y7_N2; Fanout = 1; COMB Node = 'select:inst2\|Selector2~195'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.628 ns" { ceping:inst|data[21] select:inst2|Selector2~195 } "NODE_NAME" } } { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/select.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.534 ns) + CELL(0.114 ns) 2.276 ns select:inst2\|Selector2~203 3 COMB LC_X22_Y9_N7 1 " "Info: 3: + IC(1.534 ns) + CELL(0.114 ns) = 2.276 ns; Loc. = LC_X22_Y9_N7; Fanout = 1; COMB Node = 'select:inst2\|Selector2~203'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.648 ns" { select:inst2|Selector2~195 select:inst2|Selector2~203 } "NODE_NAME" } } { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/select.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.551 ns) + CELL(0.114 ns) 3.941 ns select:inst2\|Selector2~200 4 COMB LC_X26_Y8_N5 1 " "Info: 4: + IC(1.551 ns) + CELL(0.114 ns) = 3.941 ns; Loc. = LC_X26_Y8_N5; Fanout = 1; COMB Node = 'select:inst2\|Selector2~200'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.665 ns" { select:inst2|Selector2~203 select:inst2|Selector2~200 } "NODE_NAME" } } { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/select.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.114 ns) 4.481 ns select:inst2\|Selector2~201 5 COMB LC_X26_Y8_N1 1 " "Info: 5: + IC(0.426 ns) + CELL(0.114 ns) = 4.481 ns; Loc. = LC_X26_Y8_N1; Fanout = 1; COMB Node = 'select:inst2\|Selector2~201'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.540 ns" { select:inst2|Selector2~200 select:inst2|Selector2~201 } "NODE_NAME" } } { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/select.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.546 ns) + CELL(0.590 ns) 6.617 ns select:inst2\|Selector2~202 6 COMB LC_X23_Y10_N4 7 " "Info: 6: + IC(1.546 ns) + CELL(0.590 ns) = 6.617 ns; Loc. = LC_X23_Y10_N4; Fanout = 7; COMB Node = 'select:inst2\|Selector2~202'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.136 ns" { select:inst2|Selector2~201 select:inst2|Selector2~202 } "NODE_NAME" } } { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/select.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.442 ns) 8.279 ns yima:inst3\|out~49 7 COMB LC_X23_Y7_N4 1 " "Info: 7: + IC(1.220 ns) + CELL(0.442 ns) = 8.279 ns; Loc. = LC_X23_Y7_N4; Fanout = 1; COMB Node = 'yima:inst3\|out~49'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.662 ns" { select:inst2|Selector2~202 yima:inst3|out~49 } "NODE_NAME" } } { "yima.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/yima.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.217 ns) + CELL(2.124 ns) 12.620 ns duan\[0\] 8 PIN PIN_108 0 " "Info: 8: + IC(2.217 ns) + CELL(2.124 ns) = 12.620 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'duan\[0\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "4.341 ns" { yima:inst3|out~49 duan[0] } "NODE_NAME" } } { "plvji.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.bdf" { { 208 848 1024 224 "duan\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.612 ns ( 28.62 % ) " "Info: Total cell delay = 3.612 ns ( 28.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.008 ns ( 71.38 % ) " "Info: Total interconnect delay = 9.008 ns ( 71.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "12.620 ns" { ceping:inst|data[21] select:inst2|Selector2~195 select:inst2|Selector2~203 select:inst2|Selector2~200 select:inst2|Selector2~201 select:inst2|Selector2~202 yima:inst3|out~49 duan[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "12.620 ns" { ceping:inst|data[21] select:inst2|Selector2~195 select:inst2|Selector2~203 select:inst2|Selector2~200 select:inst2|Selector2~201 select:inst2|Selector2~202 yima:inst3|out~49 duan[0] } { 0.000ns 0.514ns 1.534ns 1.551ns 0.426ns 1.546ns 1.220ns 2.217ns } { 0.000ns 0.114ns 0.114ns 0.114ns 0.114ns 0.590ns 0.442ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.493 ns" { clkx ceping:inst|data[21] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.493 ns" { clkx clkx~out0 ceping:inst|data[21] } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "12.620 ns" { ceping:inst|data[21] select:inst2|Selector2~195 select:inst2|Selector2~203 select:inst2|Selector2~200 select:inst2|Selector2~201 select:inst2|Selector2~202 yima:inst3|out~49 duan[0] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "12.620 ns" { ceping:inst|data[21] select:inst2|Selector2~195 select:inst2|Selector2~203 select:inst2|Selector2~200 select:inst2|Selector2~201 select:inst2|Selector2~202 yima:inst3|out~49 duan[0] } { 0.000ns 0.514ns 1.534ns 1.551ns 0.426ns 1.546ns 1.220ns 2.217ns } { 0.000ns 0.114ns 0.114ns 0.114ns 0.114ns 0.590ns 0.442ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 02 15:02:50 2007 " "Info: Processing ended: Sun Dec 02 15:02:50 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}