📄 plvji.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "plvji.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.bdf" { { 232 -8 160 248 "clk" "" } } } } { "d:/quartus2_setup/win/Assignment Editor.qase" "" { Assignment "d:/quartus2_setup/win/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clkx " "Info: Assuming node \"clkx\" is an undefined clock" { } { { "plvji.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.bdf" { { 248 -8 160 264 "clkx" "" } } } } { "d:/quartus2_setup/win/Assignment Editor.qase" "" { Assignment "d:/quartus2_setup/win/Assignment Editor.qase" 1 { { 0 "clkx" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register saomiao:inst1\|clkx\[5\] register ceping:inst\|count\[16\] 120.02 MHz 8.332 ns Internal " "Info: Clock \"clk\" has Internal fmax of 120.02 MHz between source register \"saomiao:inst1\|clkx\[5\]\" and destination register \"ceping:inst\|count\[16\]\" (period= 8.332 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.071 ns + Longest register register " "Info: + Longest register to register delay is 8.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns saomiao:inst1\|clkx\[5\] 1 REG LC_X19_Y11_N4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y11_N4; Fanout = 5; REG Node = 'saomiao:inst1\|clkx\[5\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { saomiao:inst1|clkx[5] } "NODE_NAME" } } { "saomiao.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/saomiao.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.564 ns) 1.831 ns ceping:inst\|Add0~473 2 COMB LC_X18_Y10_N0 2 " "Info: 2: + IC(1.267 ns) + CELL(0.564 ns) = 1.831 ns; Loc. = LC_X18_Y10_N0; Fanout = 2; COMB Node = 'ceping:inst\|Add0~473'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.831 ns" { saomiao:inst1|clkx[5] ceping:inst|Add0~473 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.909 ns ceping:inst\|Add0~475 3 COMB LC_X18_Y10_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.909 ns; Loc. = LC_X18_Y10_N1; Fanout = 2; COMB Node = 'ceping:inst\|Add0~475'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { ceping:inst|Add0~473 ceping:inst|Add0~475 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.987 ns ceping:inst\|Add0~477 4 COMB LC_X18_Y10_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.987 ns; Loc. = LC_X18_Y10_N2; Fanout = 2; COMB Node = 'ceping:inst\|Add0~477'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { ceping:inst|Add0~475 ceping:inst|Add0~477 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 2.065 ns ceping:inst\|Add0~479 5 COMB LC_X18_Y10_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 2.065 ns; Loc. = LC_X18_Y10_N3; Fanout = 2; COMB Node = 'ceping:inst\|Add0~479'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { ceping:inst|Add0~477 ceping:inst|Add0~479 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.243 ns ceping:inst\|Add0~485 6 COMB LC_X18_Y10_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 2.243 ns; Loc. = LC_X18_Y10_N4; Fanout = 6; COMB Node = 'ceping:inst\|Add0~485'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.178 ns" { ceping:inst|Add0~479 ceping:inst|Add0~485 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.451 ns ceping:inst\|Add0~491 7 COMB LC_X18_Y10_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 2.451 ns; Loc. = LC_X18_Y10_N9; Fanout = 6; COMB Node = 'ceping:inst\|Add0~491'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.208 ns" { ceping:inst|Add0~485 ceping:inst|Add0~491 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 3.130 ns ceping:inst\|Add0~498 8 COMB LC_X18_Y9_N3 2 " "Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 3.130 ns; Loc. = LC_X18_Y9_N3; Fanout = 2; COMB Node = 'ceping:inst\|Add0~498'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.679 ns" { ceping:inst|Add0~491 ceping:inst|Add0~498 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.590 ns) 4.940 ns ceping:inst\|Equal0~346 9 COMB LC_X17_Y10_N0 1 " "Info: 9: + IC(1.220 ns) + CELL(0.590 ns) = 4.940 ns; Loc. = LC_X17_Y10_N0; Fanout = 1; COMB Node = 'ceping:inst\|Equal0~346'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.810 ns" { ceping:inst|Add0~498 ceping:inst|Equal0~346 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.239 ns) + CELL(0.292 ns) 6.471 ns ceping:inst\|Equal0~350 10 COMB LC_X17_Y8_N8 9 " "Info: 10: + IC(1.239 ns) + CELL(0.292 ns) = 6.471 ns; Loc. = LC_X17_Y8_N8; Fanout = 9; COMB Node = 'ceping:inst\|Equal0~350'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.531 ns" { ceping:inst|Equal0~346 ceping:inst|Equal0~350 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.309 ns) 8.071 ns ceping:inst\|count\[16\] 11 REG LC_X17_Y10_N2 3 " "Info: 11: + IC(1.291 ns) + CELL(0.309 ns) = 8.071 ns; Loc. = LC_X17_Y10_N2; Fanout = 3; REG Node = 'ceping:inst\|count\[16\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.600 ns" { ceping:inst|Equal0~350 ceping:inst|count[16] } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.054 ns ( 37.84 % ) " "Info: Total cell delay = 3.054 ns ( 37.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.017 ns ( 62.16 % ) " "Info: Total interconnect delay = 5.017 ns ( 62.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.071 ns" { saomiao:inst1|clkx[5] ceping:inst|Add0~473 ceping:inst|Add0~475 ceping:inst|Add0~477 ceping:inst|Add0~479 ceping:inst|Add0~485 ceping:inst|Add0~491 ceping:inst|Add0~498 ceping:inst|Equal0~346 ceping:inst|Equal0~350 ceping:inst|count[16] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.071 ns" { saomiao:inst1|clkx[5] ceping:inst|Add0~473 ceping:inst|Add0~475 ceping:inst|Add0~477 ceping:inst|Add0~479 ceping:inst|Add0~485 ceping:inst|Add0~491 ceping:inst|Add0~498 ceping:inst|Equal0~346 ceping:inst|Equal0~350 ceping:inst|count[16] } { 0.000ns 1.267ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.220ns 1.239ns 1.291ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.078ns 0.178ns 0.208ns 0.679ns 0.590ns 0.292ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 34; CLK Node = 'clk'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plvji.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.bdf" { { 232 -8 160 248 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns ceping:inst\|count\[16\] 2 REG LC_X17_Y10_N2 3 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X17_Y10_N2; Fanout = 3; REG Node = 'ceping:inst\|count\[16\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk ceping:inst|count[16] } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ceping:inst|count[16] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ceping:inst|count[16] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 34; CLK Node = 'clk'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plvji.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.bdf" { { 232 -8 160 248 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns saomiao:inst1\|clkx\[5\] 2 REG LC_X19_Y11_N4 5 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X19_Y11_N4; Fanout = 5; REG Node = 'saomiao:inst1\|clkx\[5\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk saomiao:inst1|clkx[5] } "NODE_NAME" } } { "saomiao.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/saomiao.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk saomiao:inst1|clkx[5] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 saomiao:inst1|clkx[5] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ceping:inst|count[16] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ceping:inst|count[16] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk saomiao:inst1|clkx[5] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 saomiao:inst1|clkx[5] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "saomiao.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/saomiao.v" 11 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "8.071 ns" { saomiao:inst1|clkx[5] ceping:inst|Add0~473 ceping:inst|Add0~475 ceping:inst|Add0~477 ceping:inst|Add0~479 ceping:inst|Add0~485 ceping:inst|Add0~491 ceping:inst|Add0~498 ceping:inst|Equal0~346 ceping:inst|Equal0~350 ceping:inst|count[16] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "8.071 ns" { saomiao:inst1|clkx[5] ceping:inst|Add0~473 ceping:inst|Add0~475 ceping:inst|Add0~477 ceping:inst|Add0~479 ceping:inst|Add0~485 ceping:inst|Add0~491 ceping:inst|Add0~498 ceping:inst|Equal0~346 ceping:inst|Equal0~350 ceping:inst|count[16] } { 0.000ns 1.267ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.220ns 1.239ns 1.291ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.078ns 0.178ns 0.208ns 0.679ns 0.590ns 0.292ns 0.309ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ceping:inst|count[16] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ceping:inst|count[16] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk saomiao:inst1|clkx[5] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 saomiao:inst1|clkx[5] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkx register ceping:inst\|min\[6\] register ceping:inst\|min\[27\] 103.72 MHz 9.641 ns Internal " "Info: Clock \"clkx\" has Internal fmax of 103.72 MHz between source register \"ceping:inst\|min\[6\]\" and destination register \"ceping:inst\|min\[27\]\" (period= 9.641 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.380 ns + Longest register register " "Info: + Longest register to register delay is 9.380 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ceping:inst\|min\[6\] 1 REG LC_X23_Y9_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y9_N2; Fanout = 4; REG Node = 'ceping:inst\|min\[6\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { ceping:inst|min[6] } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.262 ns) + CELL(0.423 ns) 1.685 ns ceping:inst\|Add1~563 2 COMB LC_X24_Y8_N0 2 " "Info: 2: + IC(1.262 ns) + CELL(0.423 ns) = 1.685 ns; Loc. = LC_X24_Y8_N0; Fanout = 2; COMB Node = 'ceping:inst\|Add1~563'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.685 ns" { ceping:inst|min[6] ceping:inst|Add1~563 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.763 ns ceping:inst\|Add1~565 3 COMB LC_X24_Y8_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.763 ns; Loc. = LC_X24_Y8_N1; Fanout = 2; COMB Node = 'ceping:inst\|Add1~565'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { ceping:inst|Add1~563 ceping:inst|Add1~565 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.841 ns ceping:inst\|Add1~557 4 COMB LC_X24_Y8_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.841 ns; Loc. = LC_X24_Y8_N2; Fanout = 2; COMB Node = 'ceping:inst\|Add1~557'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { ceping:inst|Add1~565 ceping:inst|Add1~557 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.919 ns ceping:inst\|Add1~573 5 COMB LC_X24_Y8_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.919 ns; Loc. = LC_X24_Y8_N3; Fanout = 2; COMB Node = 'ceping:inst\|Add1~573'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.078 ns" { ceping:inst|Add1~557 ceping:inst|Add1~573 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.097 ns ceping:inst\|Add1~575 6 COMB LC_X24_Y8_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 2.097 ns; Loc. = LC_X24_Y8_N4; Fanout = 6; COMB Node = 'ceping:inst\|Add1~575'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.178 ns" { ceping:inst|Add1~573 ceping:inst|Add1~575 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.305 ns ceping:inst\|Add1~583 7 COMB LC_X24_Y8_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 2.305 ns; Loc. = LC_X24_Y8_N9; Fanout = 6; COMB Node = 'ceping:inst\|Add1~583'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.208 ns" { ceping:inst|Add1~575 ceping:inst|Add1~583 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.984 ns ceping:inst\|Add1~588 8 COMB LC_X24_Y7_N0 6 " "Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 2.984 ns; Loc. = LC_X24_Y7_N0; Fanout = 6; COMB Node = 'ceping:inst\|Add1~588'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.679 ns" { ceping:inst|Add1~583 ceping:inst|Add1~588 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(0.590 ns) 4.819 ns ceping:inst\|min\[19\]~8889 9 COMB LC_X25_Y9_N9 1 " "Info: 9: + IC(1.245 ns) + CELL(0.590 ns) = 4.819 ns; Loc. = LC_X25_Y9_N9; Fanout = 1; COMB Node = 'ceping:inst\|min\[19\]~8889'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.835 ns" { ceping:inst|Add1~588 ceping:inst|min[19]~8889 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.252 ns) + CELL(0.292 ns) 6.363 ns ceping:inst\|min\[19\]~8890 10 COMB LC_X25_Y8_N6 7 " "Info: 10: + IC(1.252 ns) + CELL(0.292 ns) = 6.363 ns; Loc. = LC_X25_Y8_N6; Fanout = 7; COMB Node = 'ceping:inst\|min\[19\]~8890'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.544 ns" { ceping:inst|min[19]~8889 ceping:inst|min[19]~8890 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.114 ns) 6.902 ns ceping:inst\|min\[23\]~8892 11 COMB LC_X25_Y8_N3 7 " "Info: 11: + IC(0.425 ns) + CELL(0.114 ns) = 6.902 ns; Loc. = LC_X25_Y8_N3; Fanout = 7; COMB Node = 'ceping:inst\|min\[23\]~8892'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.539 ns" { ceping:inst|min[19]~8890 ceping:inst|min[23]~8892 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.114 ns) 7.486 ns ceping:inst\|min\[28\]~8894 12 COMB LC_X25_Y8_N0 7 " "Info: 12: + IC(0.470 ns) + CELL(0.114 ns) = 7.486 ns; Loc. = LC_X25_Y8_N0; Fanout = 7; COMB Node = 'ceping:inst\|min\[28\]~8894'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.584 ns" { ceping:inst|min[23]~8892 ceping:inst|min[28]~8894 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 7.782 ns ceping:inst\|min\[27\]~8906 13 COMB LC_X25_Y8_N1 3 " "Info: 13: + IC(0.182 ns) + CELL(0.114 ns) = 7.782 ns; Loc. = LC_X25_Y8_N1; Fanout = 3; COMB Node = 'ceping:inst\|min\[27\]~8906'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.296 ns" { ceping:inst|min[28]~8894 ceping:inst|min[27]~8906 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.289 ns) + CELL(0.309 ns) 9.380 ns ceping:inst\|min\[27\] 14 REG LC_X24_Y6_N7 4 " "Info: 14: + IC(1.289 ns) + CELL(0.309 ns) = 9.380 ns; Loc. = LC_X24_Y6_N7; Fanout = 4; REG Node = 'ceping:inst\|min\[27\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.598 ns" { ceping:inst|min[27]~8906 ceping:inst|min[27] } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.255 ns ( 34.70 % ) " "Info: Total cell delay = 3.255 ns ( 34.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.125 ns ( 65.30 % ) " "Info: Total interconnect delay = 6.125 ns ( 65.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "9.380 ns" { ceping:inst|min[6] ceping:inst|Add1~563 ceping:inst|Add1~565 ceping:inst|Add1~557 ceping:inst|Add1~573 ceping:inst|Add1~575 ceping:inst|Add1~583 ceping:inst|Add1~588 ceping:inst|min[19]~8889 ceping:inst|min[19]~8890 ceping:inst|min[23]~8892 ceping:inst|min[28]~8894 ceping:inst|min[27]~8906 ceping:inst|min[27] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "9.380 ns" { ceping:inst|min[6] ceping:inst|Add1~563 ceping:inst|Add1~565 ceping:inst|Add1~557 ceping:inst|Add1~573 ceping:inst|Add1~575 ceping:inst|Add1~583 ceping:inst|Add1~588 ceping:inst|min[19]~8889 ceping:inst|min[19]~8890 ceping:inst|min[23]~8892 ceping:inst|min[28]~8894 ceping:inst|min[27]~8906 ceping:inst|min[27] } { 0.000ns 1.262ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.245ns 1.252ns 0.425ns 0.470ns 0.182ns 1.289ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.208ns 0.679ns 0.590ns 0.292ns 0.114ns 0.114ns 0.114ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx destination 7.493 ns + Shortest register " "Info: + Shortest clock path from clock \"clkx\" to destination register is 7.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clkx 1 CLK PIN_122 65 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 65; CLK Node = 'clkx'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clkx } "NODE_NAME" } } { "plvji.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.bdf" { { 248 -8 160 264 "clkx" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.307 ns) + CELL(0.711 ns) 7.493 ns ceping:inst\|min\[27\] 2 REG LC_X24_Y6_N7 4 " "Info: 2: + IC(5.307 ns) + CELL(0.711 ns) = 7.493 ns; Loc. = LC_X24_Y6_N7; Fanout = 4; REG Node = 'ceping:inst\|min\[27\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "6.018 ns" { clkx ceping:inst|min[27] } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.17 % ) " "Info: Total cell delay = 2.186 ns ( 29.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.307 ns ( 70.83 % ) " "Info: Total interconnect delay = 5.307 ns ( 70.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.493 ns" { clkx ceping:inst|min[27] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.493 ns" { clkx clkx~out0 ceping:inst|min[27] } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.475ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx source 7.493 ns - Longest register " "Info: - Longest clock path from clock \"clkx\" to source register is 7.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clkx 1 CLK PIN_122 65 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 65; CLK Node = 'clkx'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { clkx } "NODE_NAME" } } { "plvji.bdf" "" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.bdf" { { 248 -8 160 264 "clkx" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.307 ns) + CELL(0.711 ns) 7.493 ns ceping:inst\|min\[6\] 2 REG LC_X23_Y9_N2 4 " "Info: 2: + IC(5.307 ns) + CELL(0.711 ns) = 7.493 ns; Loc. = LC_X23_Y9_N2; Fanout = 4; REG Node = 'ceping:inst\|min\[6\]'" { } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "6.018 ns" { clkx ceping:inst|min[6] } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.17 % ) " "Info: Total cell delay = 2.186 ns ( 29.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.307 ns ( 70.83 % ) " "Info: Total interconnect delay = 5.307 ns ( 70.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.493 ns" { clkx ceping:inst|min[6] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.493 ns" { clkx clkx~out0 ceping:inst|min[6] } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.475ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.493 ns" { clkx ceping:inst|min[27] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.493 ns" { clkx clkx~out0 ceping:inst|min[27] } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.493 ns" { clkx ceping:inst|min[6] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.493 ns" { clkx clkx~out0 ceping:inst|min[6] } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.475ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 73 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "9.380 ns" { ceping:inst|min[6] ceping:inst|Add1~563 ceping:inst|Add1~565 ceping:inst|Add1~557 ceping:inst|Add1~573 ceping:inst|Add1~575 ceping:inst|Add1~583 ceping:inst|Add1~588 ceping:inst|min[19]~8889 ceping:inst|min[19]~8890 ceping:inst|min[23]~8892 ceping:inst|min[28]~8894 ceping:inst|min[27]~8906 ceping:inst|min[27] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "9.380 ns" { ceping:inst|min[6] ceping:inst|Add1~563 ceping:inst|Add1~565 ceping:inst|Add1~557 ceping:inst|Add1~573 ceping:inst|Add1~575 ceping:inst|Add1~583 ceping:inst|Add1~588 ceping:inst|min[19]~8889 ceping:inst|min[19]~8890 ceping:inst|min[23]~8892 ceping:inst|min[28]~8894 ceping:inst|min[27]~8906 ceping:inst|min[27] } { 0.000ns 1.262ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.245ns 1.252ns 0.425ns 0.470ns 0.182ns 1.289ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.208ns 0.679ns 0.590ns 0.292ns 0.114ns 0.114ns 0.114ns 0.309ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.493 ns" { clkx ceping:inst|min[27] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.493 ns" { clkx clkx~out0 ceping:inst|min[27] } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "7.493 ns" { clkx ceping:inst|min[6] } "NODE_NAME" } } { "d:/quartus2_setup/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2_setup/win/Technology_Viewer.qrui" "7.493 ns" { clkx clkx~out0 ceping:inst|min[6] } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.475ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -