plvji.map.qmsg

该文档是基于QUARTUS2_6.0的Verilog试验例程

{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "data8 select.v(17) " "Warning (10235): Verilog HDL Always Construct warning at select.v(17): variable \"data8\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/select.v" 17 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "select.v(9) " "Info (10264): Verilog HDL Case Statement information at select.v(9): all case item expressions in this case statement are onehot" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/select.v" 9 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ceping ceping:inst " "Info: Elaborating entity \"ceping\" for hierarchy \"ceping:inst\"" {  } { { "plvji.bdf" "inst" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.bdf" { { 208 192 320 304 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 31 ceping.v(13) " "Warning (10230): Verilog HDL assignment warning at ceping.v(13): truncated value with size 32 to match size of target (31)" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ceping.v(29) " "Warning (10230): Verilog HDL assignment warning at ceping.v(29): truncated value with size 32 to match size of target (4)" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ceping.v(33) " "Warning (10230): Verilog HDL assignment warning at ceping.v(33): truncated value with size 32 to match size of target (4)" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ceping.v(37) " "Warning (10230): Verilog HDL assignment warning at ceping.v(37): truncated value with size 32 to match size of target (4)" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ceping.v(41) " "Warning (10230): Verilog HDL assignment warning at ceping.v(41): truncated value with size 32 to match size of target (4)" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ceping.v(45) " "Warning (10230): Verilog HDL assignment warning at ceping.v(45): truncated value with size 32 to match size of target (4)" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ceping.v(49) " "Warning (10230): Verilog HDL assignment warning at ceping.v(49): truncated value with size 32 to match size of target (4)" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 49 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ceping.v(53) " "Warning (10230): Verilog HDL assignment warning at ceping.v(53): truncated value with size 32 to match size of target (4)" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 53 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "saomiao saomiao:inst1 " "Info: Elaborating entity \"saomiao\" for hierarchy \"saomiao:inst1\"" {  } { { "plvji.bdf" "inst1" { Schematic "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.bdf" { { 384 320 416 480 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 saomiao.v(10) " "Warning (10230): Verilog HDL assignment warning at saomiao.v(10): truncated value with size 32 to match size of target (11)" {  } { { "saomiao.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/saomiao.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "ceping:inst\|count\[0\] saomiao:inst1\|clkx\[0\] " "Info: Duplicate register \"ceping:inst\|count\[0\]\" merged to single register \"saomiao:inst1\|clkx\[0\]\"" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "ceping:inst\|count\[1\] saomiao:inst1\|clkx\[1\] " "Info: Duplicate register \"ceping:inst\|count\[1\]\" merged to single register \"saomiao:inst1\|clkx\[1\]\"" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ceping:inst\|count\[2\] saomiao:inst1\|clkx\[2\] " "Info: Duplicate register \"ceping:inst\|count\[2\]\" merged to single register \"saomiao:inst1\|clkx\[2\]\"" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ceping:inst\|count\[3\] saomiao:inst1\|clkx\[3\] " "Info: Duplicate register \"ceping:inst\|count\[3\]\" merged to single register \"saomiao:inst1\|clkx\[3\]\"" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ceping:inst\|count\[4\] saomiao:inst1\|clkx\[4\] " "Info: Duplicate register \"ceping:inst\|count\[4\]\" merged to single register \"saomiao:inst1\|clkx\[4\]\"" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ceping:inst\|count\[5\] saomiao:inst1\|clkx\[5\] " "Info: Duplicate register \"ceping:inst\|count\[5\]\" merged to single register \"saomiao:inst1\|clkx\[5\]\"" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ceping:inst\|count\[6\] saomiao:inst1\|clkx\[6\] " "Info: Duplicate register \"ceping:inst\|count\[6\]\" merged to single register \"saomiao:inst1\|clkx\[6\]\"" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ceping:inst\|count\[7\] saomiao:inst1\|clkx\[7\] " "Info: Duplicate register \"ceping:inst\|count\[7\]\" merged to single register \"saomiao:inst1\|clkx\[7\]\"" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA实验箱例程/程序/freqency/ceping.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "274 " "Info: Implemented 274 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "257 " "Info: Implemented 257 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 02 15:02:41 2007 " "Info: Processing ended: Sun Dec 02 15:02:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.map.smsg " "Info: Generated suppressed messages file F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}