plvji.map.rpt

该文档是基于QUARTUS2_6.0的Verilog试验例程

; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 79    ;
;     -- 3 input functions                    ; 23    ;
;     -- 2 input functions                    ; 104   ;
;     -- 1 input functions                    ; 3     ;
;     -- 0 input functions                    ; 1     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 188   ;
;     -- arithmetic mode                      ; 69    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 1     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 99    ;
; Total logic cells in carry chains           ; 72    ;
; I/O pins                                    ; 17    ;
; Maximum fan-out node                        ; clkx  ;
; Maximum fan-out                             ; 65    ;
; Total fan-out                               ; 822   ;
; Average fan-out                             ; 3.00  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                            ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name  ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
; |plvji                     ; 257 (0)     ; 99           ; 0           ; 0    ; 17   ; 0            ; 158 (0)      ; 47 (0)            ; 52 (0)           ; 72 (0)          ; 0 (0)      ; |plvji               ;
;    |ceping:inst|           ; 198 (198)   ; 89           ; 0           ; 0    ; 0    ; 0            ; 109 (109)    ; 47 (47)           ; 42 (42)          ; 63 (63)         ; 0 (0)      ; |plvji|ceping:inst   ;
;    |saomiao:inst1|         ; 18 (18)     ; 10           ; 0           ; 0    ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 10 (10)          ; 9 (9)           ; 0 (0)      ; |plvji|saomiao:inst1 ;
;    |select:inst2|          ; 34 (34)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 34 (34)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |plvji|select:inst2  ;
;    |yima:inst3|            ; 7 (7)       ; 0            ; 0           ; 0    ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |plvji|yima:inst3    ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 99    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 64    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |plvji|ceping:inst|min[3]     ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |plvji|ceping:inst|min[7]     ;
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |plvji|ceping:inst|min[11]    ;
; 7:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |plvji|ceping:inst|min[13]    ;
; 8:1                ; 4 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; Yes        ; |plvji|ceping:inst|min[19]    ;
; 9:1                ; 4 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |plvji|ceping:inst|min[23]    ;
; 10:1               ; 4 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |plvji|ceping:inst|min[27]    ;
; 11:1               ; 4 bits    ; 28 LEs        ; 8 LEs                ; 20 LEs                 ; Yes        ; |plvji|ceping:inst|min[28]    ;
; 256:1              ; 4 bits    ; 680 LEs       ; 36 LEs               ; 644 LEs                ; No         ; |plvji|select:inst2|Selector3 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Dec 02 15:02:38 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off plvji -c plvji
Info: Found 1 design units, including 1 entities, in source file ceping.v
    Info: Found entity 1: ceping
Info: Found 1 design units, including 1 entities, in source file saomiao.v
    Info: Found entity 1: saomiao
Info: Found 1 design units, including 1 entities, in source file select.v
    Info: Found entity 1: select
Info: Found 1 design units, including 1 entities, in source file yima.v
    Info: Found entity 1: yima
Info: Found 1 design units, including 1 entities, in source file plvji.bdf
    Info: Found entity 1: plvji
Info: Elaborating entity "plvji" for the top level hierarchy
Info: Elaborating entity "yima" for hierarchy "yima:inst3"
Info: Elaborating entity "select" for hierarchy "select:inst2"
Warning (10235): Verilog HDL Always Construct warning at select.v(10): variable "data1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at select.v(11): variable "data2" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at select.v(12): variable "data3" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at select.v(13): variable "data4" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at select.v(14): variable "data5" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at select.v(15): variable "data6" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at select.v(16): variable "data7" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at select.v(17): variable "data8" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info (10264): Verilog HDL Case Statement information at select.v(9): all case item expressions in this case statement are onehot
Info: Elaborating entity "ceping" for hierarchy "ceping:inst"
Warning (10230): Verilog HDL assignment warning at ceping.v(13): truncated value with size 32 to match size of target (31)
Warning (10230): Verilog HDL assignment warning at ceping.v(29): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at ceping.v(33): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at ceping.v(37): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at ceping.v(41): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at ceping.v(45): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at ceping.v(49): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at ceping.v(53): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "saomiao" for hierarchy "saomiao:inst1"
Warning (10230): Verilog HDL assignment warning at saomiao.v(10): truncated value with size 32 to match size of target (11)
Info: Duplicate registers merged to single register
    Info: Duplicate register "ceping:inst|count[0]" merged to single register "saomiao:inst1|clkx[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "ceping:inst|count[1]" merged to single register "saomiao:inst1|clkx[1]"
    Info: Duplicate register "ceping:inst|count[2]" merged to single register "saomiao:inst1|clkx[2]"
    Info: Duplicate register "ceping:inst|count[3]" merged to single register "saomiao:inst1|clkx[3]"
    Info: Duplicate register "ceping:inst|count[4]" merged to single register "saomiao:inst1|clkx[4]"
    Info: Duplicate register "ceping:inst|count[5]" merged to single register "saomiao:inst1|clkx[5]"
    Info: Duplicate register "ceping:inst|count[6]" merged to single register "saomiao:inst1|clkx[6]"
    Info: Duplicate register "ceping:inst|count[7]" merged to single register "saomiao:inst1|clkx[7]"
Info: Implemented 274 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 15 output pins
    Info: Implemented 257 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings
    Info: Processing ended: Sun Dec 02 15:02:41 2007
    Info: Elapsed time: 00:00:03


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in F:/wangbin/例程/EDA实验箱例程/程序/freqency/plvji.map.smsg.