新建 文本文档 (3).txt

CPLD可编程逻辑芯片上实现信号发生器的方法和步骤

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;

entity mplayer is
  port(k     :in std_logic_vector(18 downto 3);
       clk   :in std_logic;
       preset:in std_logic;
       ch    :out std_logic;
       q     :out std_logic_vector(15 downto 0));
end mplayer;

architecture mpl_arc of mplayer is

component dff1
  port(clk,preset:in std_logic;
       k:in std_logic_vector(18 downto 3);
       q1:out std_logic_vector(15 downto 0));
end component;

component keycoder
  port(q1    :in std_logic_vector(15 downto 0);
       clk,preset:in std_logic;
       cs    :out std_logic;
       d1    :out integer range 0 to 10204);
end component;

component musiccoder
  port(clk,preset:in std_logic;
       d2 :out integer range 0 to 10204);
end component;

component liexz
  port(clk,preset:in std_logic;
       sel:out std_logic_vector(3 downto 0));
end component;

component jishi
  port(clk,preset:in std_logic;
       b:out integer range 0 to 55);
end component;

component play
  port(cs   :in std_logic;
       d1,d2:in integer range 0 to 10204;
       sel  :in std_logic_vector(3 downto 0);
       b    :in integer range 0 to 55;
    q :out std_logic_vector(15 downto 0);
    do :out integer range 0 to 10204);
end component;

component xiang
  port(do :in integer range 0 to 10204;
       clk,preset:in std_logic;
       ch :out std_logic);
end component;

signal q1          :std_logic_vector(15 downto 0);
signal cs          :std_logic;
signal d1,d2,do    :integer range 0 to 10204;
signal sel         :std_logic_vector(3 downto 0);
signal b           :integer range 0 to 55;

begin
   u1:dff1       port map(clk,preset,k,q1);
   u2:keycoder   port map(q1,clk,preset,cs,d1);
   u3:musiccoder port map(clk,preset,d2);
   u4:liexz      port map(clk,preset,sel);
   u5:jishi      port map(clk,preset,b);
   u6:play       port map(cs,d1,d2,sel,b,q,do);
   u7:xiang      port map(do,clk,preset,ch);
end;
底层模块：
1、	D触发器：
library ieee;
use ieee.std_logic_1164.all;
entity dff1 is
  port(clk,preset:in std_logic;
      k:in std_logic_vector(18 downto 3);
       q1:out std_logic_vector(15 downto 0));
end dff1;
architecture dff_arc of dff1 is
begin
  process(clk,preset)
  begin
    if preset='1' then
        q1<="1111111111111111";
    elsif clk'event and clk='1'then
        q1<=k(18 downto 3);
    end if;
  end process;
end dff_arc;
2、	键盘编码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity keycoder is
  port(q1  :in std_logic_vector(15 downto 0);
       clk,preset:in std_logic;
       cs:out bit;
       d1:out integer range 0 to 10204);
end keycoder;
architecture keycoder_arc of keycoder is
signal scan:std_logic_vector(15 downto 0);
begin
p1:
  process(clk,preset,scan)
  begin
    if preset='1'then
       scan<="1111111111111111";
    elsif clk'event and clk='1'then
      scan<=q1; 
    end if;
  end process p1; 
p2:
  process(scan)
  begin   
    case scan is
      when"1111111111111110"=>d1<=10204;          when"1111111111111101"=>d1<=9095;      when"1111111111111011"=>d1<=8065;      when"1111111111110111"=>d1<=7634;      when"1111111111101111"=>d1<=6803;      when"1111111111011111"=>d1<=6061;      when"1111111110111111"=>d1<=5714;      when"1111111101111111"=>d1<=5089;      when"1111111011111111"=>d1<=4535;      when"1111110111111111"=>d1<=4032;      when"1111101111111111"=>d1<=3396;      when"1111011111111111"=>d1<=3809;      when"1110111111111111"=>d1<=3026;      when"1101111111111111"=>d1<=2857;      when"1011111111111111"=>cs<='1';      when"0111111111111111"=>cs<='0';
      when others=>
    end case;
  end process p2;
end keycoder_arc;
3、	乐曲编码：
library ieee;
use ieee.std_logic_1164.all;
entity musiccoder is
  port(clk,preset:in std_logic;
       d2:out integer range 0 to 10204);
end musiccoder;
architecture mus_arc of musiccoder is
begin
  process(clk,preset)
  variable cnt1:integer range 0 to 1000000;
  variable cnt2:integer range 0 to 7;
  variable n:integer range 0 to 45;
  begin
    if preset='1'then
       cnt1:=0;cnt2:=0;n:=0;
    elsif clk'event and clk='1' then
      if cnt1<1000000 then
          cnt1:=cnt1+1;
        case n is
          when 0=>d2<=10204;  
                  if cnt2<1 then  
                      cnt2:=cnt2+1;
                  else
                    cnt2:=0;
                    n:=1;
                  end if;
          when 1=>d2<=7634;
                  if cnt2<5 then
                      cnt2:=cnt2+1;
                  else
                    cnt2:=0;
                    n:=2;
                  end if;
          when 2=>d2<=6061;
                  if cnt2<1 then
                      cnt2:=cnt2+1;
                  else
                    cnt2:=0;
                    n:=3;
                  end if;
          when 3=>d2<=6803;
                  if cnt2<2 then
                      cnt2:=cnt2+1;
                  else
                    cnt2:=0;
                    n:=4;
                  end if;
          when 4=>d2<=7634;
                   n:=5;
          when 5=>d2<=6803;
                  if cnt2<1 then
                      cnt2:=cnt2+1;
                  else
                    cnt2:=0;
                    n:=6;
                  end if;      
          when 6=>d2<=6061;
                  if cnt2<1 then
                      cnt2:=cnt2+1;
                  else
                    cnt2:=0;
                    n:=7;
                  end if;
          when 7=>d2<=7634;
                  if cnt2<3 then
                      cnt2:=cnt2+1;
                  else
                    cnt2:=0;
                    n:=8;
                  end if;
          when 8=>d2<=6061;
                  if cnt2<1 then
                      cnt2:=cnt2+1;
                  else
                    cnt2:=0;
                    n:=9;
                  end if;
          when 9=>d2<=5089;
                  if cnt2<1 then
                      cnt2:=cnt2+1;