control.vhd

Implement the Matrix function about 16bits on FPGA BOARD

-- ============================================================
-- File Name: control.vhd
-- ============================================================

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY control IS 
	PORT
	(
		clk		: IN STD_LOGIC;
		rst		: IN STD_LOGIC;
		dim_M	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		dim_N	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		dim_K	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		en_a	: OUT STD_LOGIC;
		en_b	: OUT STD_LOGIC;
		en_alu	: OUT STD_LOGIC;
		clr_alu	: OUT STD_LOGIC;
		addr_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		addr_b	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END control;

ARCHITECTURE behavior OF control IS

	TYPE ctrl_state IS (S0, S1, S2, S3);
	SIGNAL state : ctrl_state;
	SIGNAL int_m, int_n, int_k : INTEGER;
	SIGNAL int_a, int_b : INTEGER;

BEGIN

	int_m <= CONV_INTEGER(dim_M);
	int_n <= CONV_INTEGER(dim_N);
	int_k <= CONV_INTEGER(dim_K);
	
	addr_a <= CONV_STD_LOGIC_VECTOR(int_a, 8);
	addr_b <= CONV_STD_LOGIC_VECTOR(int_b, 8);

	PROCESS (clk, rst)
		VARIABLE i, j, l : INTEGER;
	BEGIN
		IF (rst = '1') THEN
			en_a <= '0';
			en_b <= '0';
			en_alu <= '0';
			clr_alu <= '1';
			int_a <= 0;
			int_b <= 0;
			i := 0;
			j := 0;
			l := 0;
			state <= S0;
		ELSIF (clk'EVENT AND clk = '1') THEN
			CASE state IS
				WHEN S0 =>	en_a <= '1';
							en_b <= '1';
							en_alu <= '0';
							clr_alu <= '0';
							int_a <= int_k * l + j;
							int_b <= int_n * j + i; 
							state <= S1;
				WHEN S1 =>	en_a <= '0';
							en_b <= '0';
							en_alu <= '1';
							clr_alu <= '0';
							state <= S2;
				WHEN S2 =>	en_a <= '0';
							en_b <= '0';
							en_alu <= '0';
							j := j + 1;
							IF (j = int_k) THEN
								i := i + 1;
								j := 0;
								clr_alu <= '1';
							ELSE
								clr_alu <= '0';
							END IF;
							IF (i = int_n) THEN
								i := 0;
								l := l + 1;
							END IF;
							IF (l = int_m) THEN
								state <= S3;
							ELSE
								state <= S0;
							END IF;
				WHEN S3 =>	en_a <= '0';
							en_b <= '0';
							en_alu <= '0';
							clr_alu <= '0';
							int_a <= 0;
							int_b <= 0;
							i := 0;
							j := 0;
							l := 0;
			END CASE;
		END IF;
	END PROCESS;

END behavior;