ram_ro_b.vhd

Implement the Matrix function about 16bits on FPGA BOARD

-- ============================================================
-- File Name: ram_ro_a.vhd
-- ============================================================

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ram_ro_b IS
	PORT 
	(
		clk		: IN STD_LOGIC;
		rst		: IN STD_LOGIC;
		en		: IN STD_LOGIC;
		addr	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END ram_ro_b;

ARCHITECTURE behavior OF ram_ro_b IS
	
	SUBTYPE word IS STD_LOGIC_VECTOR(7 DOWNTO 0);
	TYPE ram IS ARRAY(0 TO 63) OF word;	
	SIGNAL ram_ro		: RAM;
	SIGNAL addr_index	: INTEGER;
	
BEGIN

	addr_index <= CONV_INTEGER(addr);
	
	PROCESS (rst, clk)
	BEGIN
		IF (rst = '1') THEN
			FOR i IN 0 TO 63 LOOP
				ram_ro(i) <= CONV_STD_LOGIC_VECTOR(i + 7, 8);
			END LOOP;
		ELSIF (clk'EVENT AND clk = '0' AND en = '1') THEN 
			dout <= ram_ro(addr_index);
		END IF;
	END PROCESS;
		
END behavior;