alu.vhd

Implement the Matrix function about 16bits on FPGA BOARD

-- ============================================================
-- File Name: alu.vhd
-- ============================================================

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY alu IS 
	PORT
	(
		clk		: IN STD_LOGIC;
		clr		: IN STD_LOGIC;
		en		: IN STD_LOGIC;
		din_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		din_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
END alu;

ARCHITECTURE behavior OF alu IS
	
	TYPE ctrl_state IS (S0, S1);
	SIGNAL state	: ctrl_state;
	SIGNAL temp2, temp3 : STD_LOGIC_VECTOR (15 DOWNTO 0);

BEGIN

	dout <= temp3 WHEN clr = '1';
	
	PROCESS (clk)
		VARIABLE temp1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
	BEGIN

		IF (clk'EVENT AND clk = '0') THEN
			IF (clr = '1') THEN
				temp2 <= "0000000000000000";
				state <= S0;
			ELSIF (en = '1') THEN
				CASE state IS
					WHEN S0 =>	temp1 := din_a * din_b;
								temp3 <= temp1 + temp2;
								state <= S1;
					WHEN S1 =>	temp2 <= temp3;
				END CASE;
			ELSE
				state <= S0;
			END IF;	
		END IF;

	END PROCESS;

END behavior;