matrix_multiply.vhd

Implement the Matrix function about 16bits on FPGA BOARD

-- ============================================================
-- File Name: matrix_multiply.vhd
-- ============================================================

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY matrix_multiply IS 
	PORT
	(
		clk		: IN STD_LOGIC;
		rst		: IN STD_LOGIC;
		dim_M	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		dim_N	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		dim_K	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END matrix_multiply;

ARCHITECTURE structure OF matrix_multiply IS

COMPONENT ram_ro_a
	PORT 
	(
		clk		: IN STD_LOGIC;
		rst		: IN STD_LOGIC;
		en		: IN STD_LOGIC;
		addr	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

COMPONENT ram_ro_b
	PORT 
	(
		clk		: IN STD_LOGIC;
		rst		: IN STD_LOGIC;
		en		: IN STD_LOGIC;
		addr	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

COMPONENT alu
	PORT
	(
		clk		: IN STD_LOGIC;
		clr		: IN STD_LOGIC;
		en		: IN STD_LOGIC;
		din_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		din_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
END COMPONENT;

COMPONENT PLL
	PORT
	(
		inclk0	: IN STD_LOGIC;
		c0		: OUT STD_LOGIC 
	);
END COMPONENT;

COMPONENT control 
	PORT
	(
		clk		: IN STD_LOGIC;
		rst		: IN STD_LOGIC;
		dim_M	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		dim_N	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		dim_K	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		en_a	: OUT STD_LOGIC;
		en_b	: OUT STD_LOGIC;
		en_alu	: OUT STD_LOGIC;
		clr_alu	: OUT STD_LOGIC;
		addr_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		addr_b	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

SIGNAL r_clk, r_clr_alu : STD_LOGIC;
SIGNAL r_en_a, r_en_b, r_en_alu	: STD_LOGIC;
SIGNAL r_addr_a, r_addr_b : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL r_dout_a, r_dout_b : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL r_dout_alu : STD_LOGIC_VECTOR (15 DOWNTO 0);

BEGIN

	dout <= r_dout_alu;

	U0 : ram_ro_a PORT MAP(clk, rst, r_en_a, r_addr_a, r_dout_a);
	U1 : ram_ro_b PORT MAP(clk, rst, r_en_b, r_addr_b, r_dout_b);
	U2 : control PORT MAP(clk, rst, dim_M, dim_N, dim_K, r_en_a, r_en_b, r_en_alu, r_clr_alu, r_addr_a, r_addr_b);
	U3 : PLL PORT MAP(clk, r_clk);
	U4 : alu PORT MAP(r_clk, r_clr_alu, r_en_alu, r_dout_a, r_dout_b, r_dout_alu);
		
END structure;