📄 control.vwf

📁 Implement the Matrix function about 16bits on FPGA BOARD
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	DATA_OFFSET = 0.0;
	DATA_DURATION = 1000.0;
	SIMULATION_TIME = 0.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

USER_TYPE("__state")
{
	VALUES = "Undefined";
}

SIGNAL("addr_a")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("addr_a[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_a";
}

SIGNAL("addr_a[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_a";
}

SIGNAL("addr_a[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_a";
}

SIGNAL("addr_a[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_a";
}

SIGNAL("addr_a[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_a";
}

SIGNAL("addr_a[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_a";
}

SIGNAL("addr_a[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_a";
}

SIGNAL("addr_a[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_a";
}

SIGNAL("addr_b")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("addr_b[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_b";
}

SIGNAL("addr_b[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_b";
}

SIGNAL("addr_b[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_b";
}

SIGNAL("addr_b[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_b";
}

SIGNAL("addr_b[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_b";
}

SIGNAL("addr_b[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_b";
}

SIGNAL("addr_b[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_b";
}

SIGNAL("addr_b[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "addr_b";
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("clr_alu")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("dim_K")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 3;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("dim_K[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "dim_K";
}

SIGNAL("dim_K[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "dim_K";
}

SIGNAL("dim_K[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "dim_K";
}

SIGNAL("dim_M")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 3;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("dim_M[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "dim_M";
}

SIGNAL("dim_M[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "dim_M";
}

SIGNAL("dim_M[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "dim_M";
}

SIGNAL("dim_N")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 3;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("dim_N[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "dim_N";
}

SIGNAL("dim_N[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "dim_N";
}

SIGNAL("dim_N[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "dim_N";
}

SIGNAL("en_a")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("en_alu")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("en_b")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("rst")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

TRANSITION_LIST("addr_a[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_a[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_a[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_a[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_a[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_a[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_a[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_a[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_b[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_b[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_b[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_b[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_b[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_b[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_b[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("addr_b[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 66;
			LEVEL 0 FOR 7.5;
			LEVEL 1 FOR 7.5;
		}
		LEVEL 0 FOR 7.5;
		LEVEL 1 FOR 2.5;
	}
}

TRANSITION_LIST("clr_alu")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("dim_K[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("dim_K[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("dim_K[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("dim_M[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("dim_M[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("dim_M[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("dim_N[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("dim_N[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("dim_N[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("en_a")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("en_alu")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("en_b")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("rst")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 0.2;
		LEVEL 1 FOR 17.0;
		LEVEL 0 FOR 982.8;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rst";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "dim_M";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
	CHILDREN = 3, 4, 5;
}

DISPLAY_LINE
{
	CHANNEL = "dim_M[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "dim_M[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "dim_M[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "dim_K";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 6;
	TREE_LEVEL = 0;
	CHILDREN = 7, 8, 9;
}

DISPLAY_LINE
{
	CHANNEL = "dim_K[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 6;
}

DISPLAY_LINE
{
	CHANNEL = "dim_K[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 6;
}

DISPLAY_LINE
{
	CHANNEL = "dim_K[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 6;
}

DISPLAY_LINE
{
	CHANNEL = "dim_N";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 10;
	TREE_LEVEL = 0;
	CHILDREN = 11, 12, 13;
}

DISPLAY_LINE
{
	CHANNEL = "dim_N[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "dim_N[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "dim_N[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "en_a";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 14;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "en_b";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 15;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clr_alu";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 16;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "en_alu";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 17;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "addr_a";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 18;
	TREE_LEVEL = 0;
	CHILDREN = 19, 20, 21, 22, 23, 24, 25, 26;
}

DISPLAY_LINE
{
	CHANNEL = "addr_a[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "addr_a[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "addr_a[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "addr_a[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "addr_a[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "addr_a[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "addr_a[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "addr_a[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "addr_b";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 27;
	TREE_LEVEL = 0;
	CHILDREN = 28, 29, 30, 31, 32, 33, 34, 35;
}

DISPLAY_LINE
{
	CHANNEL = "addr_b[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 27;
}

DISPLAY_LINE
{
	CHANNEL = "addr_b[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 27;
}

DISPLAY_LINE
{
	CHANNEL = "addr_b[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 30;
	TREE_LEVEL = 1;
	PARENT = 27;
}

DISPLAY_LINE
{
	CHANNEL = "addr_b[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 31;
	TREE_LEVEL = 1;
	PARENT = 27;
}

DISPLAY_LINE
{
	CHANNEL = "addr_b[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 32;
	TREE_LEVEL = 1;
	PARENT = 27;
}

DISPLAY_LINE
{
	CHANNEL = "addr_b[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 33;
	TREE_LEVEL = 1;
	PARENT = 27;
}

DISPLAY_LINE
{
	CHANNEL = "addr_b[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 34;
	TREE_LEVEL = 1;
	PARENT = 27;
}

DISPLAY_LINE
{
	CHANNEL = "addr_b[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Signed;
	TREE_INDEX = 35;
	TREE_LEVEL = 1;
	PARENT = 27;
}

TIME_BAR
{
	TIME = 17100;
	MASTER = TRUE;
}
;
💿 文件大小 14 K
👤 上传用户 hqbbsw
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#Implement #function #Matrix #BOARD
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