prev_cmp_twice.tan.qmsg

用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真

{ "Info" "ITDB_FULL_TPD_RESULT" "clk clk_out 5.141 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"clk_out\" is 5.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.150 ns) 1.765 ns clk_temp~0 2 COMB LCCOMB_X30_Y35_N2 2 " "Info: 2: + IC(0.636 ns) + CELL(0.150 ns) = 1.765 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.786 ns" { clk clk_temp~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.578 ns) + CELL(2.798 ns) 5.141 ns clk_out 3 PIN PIN_B11 0 " "Info: 3: + IC(0.578 ns) + CELL(2.798 ns) = 5.141 ns; Loc. = PIN_B11; Fanout = 0; PIN Node = 'clk_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.376 ns" { clk_temp~0 clk_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.927 ns ( 76.39 % ) " "Info: Total cell delay = 3.927 ns ( 76.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.214 ns ( 23.61 % ) " "Info: Total interconnect delay = 1.214 ns ( 23.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.141 ns" { clk clk_temp~0 clk_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "5.141 ns" { clk {} clk~combout {} clk_temp~0 {} clk_out {} } { 0.000ns 0.000ns 0.636ns 0.578ns } { 0.000ns 0.979ns 0.150ns 2.798ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "d_out rst clk 0.952 ns register " "Info: th for register \"d_out\" (data pin = \"rst\", clock pin = \"clk\") is 0.952 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.535 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.150 ns) 1.765 ns clk_temp~0 2 COMB LCCOMB_X30_Y35_N2 2 " "Info: 2: + IC(0.636 ns) + CELL(0.150 ns) = 1.765 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.786 ns" { clk clk_temp~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.233 ns) + CELL(0.537 ns) 2.535 ns d_out 3 REG LCFF_X30_Y35_N1 2 " "Info: 3: + IC(0.233 ns) + CELL(0.537 ns) = 2.535 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.770 ns" { clk_temp~0 d_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.666 ns ( 65.72 % ) " "Info: Total cell delay = 1.666 ns ( 65.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.869 ns ( 34.28 % ) " "Info: Total interconnect delay = 0.869 ns ( 34.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk clk_temp~0 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.535 ns" { clk {} clk~combout {} clk_temp~0 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.233ns } { 0.000ns 0.979ns 0.150ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.849 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns rst 1 PIN PIN_D13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; PIN Node = 'rst'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.150 ns) 1.765 ns d_out~11 2 COMB LCCOMB_X30_Y35_N0 1 " "Info: 2: + IC(0.636 ns) + CELL(0.150 ns) = 1.765 ns; Loc. = LCCOMB_X30_Y35_N0; Fanout = 1; COMB Node = 'd_out~11'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.786 ns" { rst d_out~11 } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.849 ns d_out 3 REG LCFF_X30_Y35_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.849 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { d_out~11 d_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.213 ns ( 65.60 % ) " "Info: Total cell delay = 1.213 ns ( 65.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.636 ns ( 34.40 % ) " "Info: Total interconnect delay = 0.636 ns ( 34.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.849 ns" { rst d_out~11 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "1.849 ns" { rst {} rst~combout {} d_out~11 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk clk_temp~0 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.535 ns" { clk {} clk~combout {} clk_temp~0 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.233ns } { 0.000ns 0.979ns 0.150ns 0.537ns } "" } } { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.849 ns" { rst d_out~11 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "1.849 ns" { rst {} rst~combout {} d_out~11 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Peak virtual memory: 125 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 22 10:42:12 2008 " "Info: Processing ended: Mon Dec 22 10:42:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}