prev_cmp_twice.tan.qmsg

用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "clk_temp~0 " "Info: Detected gated clock \"clk_temp~0\" as buffer" {  } { { "d:/eda/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/eda/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_temp~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "d_out " "Info: Detected ripple clock \"d_out\" as buffer" {  } { { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } } { "d:/eda/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/eda/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "d_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register d_out d_out 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"d_out\" and destination register \"d_out\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Longest register register " "Info: + Longest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d_out 1 REG LCFF_X30_Y35_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { d_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns d_out~11 2 COMB LCCOMB_X30_Y35_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X30_Y35_N0; Fanout = 1; COMB Node = 'd_out~11'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.323 ns" { d_out d_out~11 } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns d_out 3 REG LCFF_X30_Y35_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { d_out~11 d_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.407 ns" { d_out d_out~11 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "0.407 ns" { d_out {} d_out~11 {} d_out {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.535 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.150 ns) 1.765 ns clk_temp~0 2 COMB LCCOMB_X30_Y35_N2 2 " "Info: 2: + IC(0.636 ns) + CELL(0.150 ns) = 1.765 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.786 ns" { clk clk_temp~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.233 ns) + CELL(0.537 ns) 2.535 ns d_out 3 REG LCFF_X30_Y35_N1 2 " "Info: 3: + IC(0.233 ns) + CELL(0.537 ns) = 2.535 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.770 ns" { clk_temp~0 d_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.666 ns ( 65.72 % ) " "Info: Total cell delay = 1.666 ns ( 65.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.869 ns ( 34.28 % ) " "Info: Total interconnect delay = 0.869 ns ( 34.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk clk_temp~0 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.535 ns" { clk {} clk~combout {} clk_temp~0 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.233ns } { 0.000ns 0.979ns 0.150ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.535 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.150 ns) 1.765 ns clk_temp~0 2 COMB LCCOMB_X30_Y35_N2 2 " "Info: 2: + IC(0.636 ns) + CELL(0.150 ns) = 1.765 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.786 ns" { clk clk_temp~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.233 ns) + CELL(0.537 ns) 2.535 ns d_out 3 REG LCFF_X30_Y35_N1 2 " "Info: 3: + IC(0.233 ns) + CELL(0.537 ns) = 2.535 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.770 ns" { clk_temp~0 d_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.666 ns ( 65.72 % ) " "Info: Total cell delay = 1.666 ns ( 65.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.869 ns ( 34.28 % ) " "Info: Total interconnect delay = 0.869 ns ( 34.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk clk_temp~0 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.535 ns" { clk {} clk~combout {} clk_temp~0 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.233ns } { 0.000ns 0.979ns 0.150ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk clk_temp~0 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.535 ns" { clk {} clk~combout {} clk_temp~0 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.233ns } { 0.000ns 0.979ns 0.150ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.407 ns" { d_out d_out~11 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "0.407 ns" { d_out {} d_out~11 {} d_out {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } } { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk clk_temp~0 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.535 ns" { clk {} clk~combout {} clk_temp~0 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.233ns } { 0.000ns 0.979ns 0.150ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { d_out {} } {  } {  } "" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "d_out rst clk -0.722 ns register " "Info: tsu for register \"d_out\" (data pin = \"rst\", clock pin = \"clk\") is -0.722 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.849 ns + Longest pin register " "Info: + Longest pin to register delay is 1.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns rst 1 PIN PIN_D13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; PIN Node = 'rst'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.150 ns) 1.765 ns d_out~11 2 COMB LCCOMB_X30_Y35_N0 1 " "Info: 2: + IC(0.636 ns) + CELL(0.150 ns) = 1.765 ns; Loc. = LCCOMB_X30_Y35_N0; Fanout = 1; COMB Node = 'd_out~11'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.786 ns" { rst d_out~11 } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.849 ns d_out 3 REG LCFF_X30_Y35_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.849 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { d_out~11 d_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.213 ns ( 65.60 % ) " "Info: Total cell delay = 1.213 ns ( 65.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.636 ns ( 34.40 % ) " "Info: Total interconnect delay = 0.636 ns ( 34.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.849 ns" { rst d_out~11 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "1.849 ns" { rst {} rst~combout {} d_out~11 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.535 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.150 ns) 1.765 ns clk_temp~0 2 COMB LCCOMB_X30_Y35_N2 2 " "Info: 2: + IC(0.636 ns) + CELL(0.150 ns) = 1.765 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.786 ns" { clk clk_temp~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.233 ns) + CELL(0.537 ns) 2.535 ns d_out 3 REG LCFF_X30_Y35_N1 2 " "Info: 3: + IC(0.233 ns) + CELL(0.537 ns) = 2.535 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.770 ns" { clk_temp~0 d_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.666 ns ( 65.72 % ) " "Info: Total cell delay = 1.666 ns ( 65.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.869 ns ( 34.28 % ) " "Info: Total interconnect delay = 0.869 ns ( 34.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk clk_temp~0 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.535 ns" { clk {} clk~combout {} clk_temp~0 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.233ns } { 0.000ns 0.979ns 0.150ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.849 ns" { rst d_out~11 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "1.849 ns" { rst {} rst~combout {} d_out~11 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } "" } } { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk clk_temp~0 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.535 ns" { clk {} clk~combout {} clk_temp~0 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.233ns } { 0.000ns 0.979ns 0.150ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_out d_out 6.881 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_out\" through register \"d_out\" is 6.881 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.535 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.150 ns) 1.765 ns clk_temp~0 2 COMB LCCOMB_X30_Y35_N2 2 " "Info: 2: + IC(0.636 ns) + CELL(0.150 ns) = 1.765 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.786 ns" { clk clk_temp~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.233 ns) + CELL(0.537 ns) 2.535 ns d_out 3 REG LCFF_X30_Y35_N1 2 " "Info: 3: + IC(0.233 ns) + CELL(0.537 ns) = 2.535 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.770 ns" { clk_temp~0 d_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.666 ns ( 65.72 % ) " "Info: Total cell delay = 1.666 ns ( 65.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.869 ns ( 34.28 % ) " "Info: Total interconnect delay = 0.869 ns ( 34.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk clk_temp~0 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.535 ns" { clk {} clk~combout {} clk_temp~0 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.233ns } { 0.000ns 0.979ns 0.150ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.096 ns + Longest register pin " "Info: + Longest register to pin delay is 4.096 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d_out 1 REG LCFF_X30_Y35_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { d_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.420 ns) 0.720 ns clk_temp~0 2 COMB LCCOMB_X30_Y35_N2 2 " "Info: 2: + IC(0.300 ns) + CELL(0.420 ns) = 0.720 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.720 ns" { d_out clk_temp~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.578 ns) + CELL(2.798 ns) 4.096 ns clk_out 3 PIN PIN_B11 0 " "Info: 3: + IC(0.578 ns) + CELL(2.798 ns) = 4.096 ns; Loc. = PIN_B11; Fanout = 0; PIN Node = 'clk_out'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.376 ns" { clk_temp~0 clk_out } "NODE_NAME" } } { "twice.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.218 ns ( 78.56 % ) " "Info: Total cell delay = 3.218 ns ( 78.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.878 ns ( 21.44 % ) " "Info: Total interconnect delay = 0.878 ns ( 21.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.096 ns" { d_out clk_temp~0 clk_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "4.096 ns" { d_out {} clk_temp~0 {} clk_out {} } { 0.000ns 0.300ns 0.578ns } { 0.000ns 0.420ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk clk_temp~0 d_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.535 ns" { clk {} clk~combout {} clk_temp~0 {} d_out {} } { 0.000ns 0.000ns 0.636ns 0.233ns } { 0.000ns 0.979ns 0.150ns 0.537ns } "" } } { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.096 ns" { d_out clk_temp~0 clk_out } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "4.096 ns" { d_out {} clk_temp~0 {} clk_out {} } { 0.000ns 0.300ns 0.578ns } { 0.000ns 0.420ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}