twice.map.summary

来自「用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Mon Dec 22 10:43:37 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
Revision Name : twice
Top-level Entity Name : twice
Family : Cyclone II
Total logic elements : 2
    Total combinational functions : 2
    Dedicated logic registers : 1
Total registers : 1
Total pins : 2
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0