twice.fit.summary

来自「用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Mon Dec 22 10:43:59 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
Revision Name : twice
Top-level Entity Name : twice
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 2 / 33,216 ( < 1 % )
    Total combinational functions : 2 / 33,216 ( < 1 % )
    Dedicated logic registers : 1 / 33,216 ( < 1 % )
Total registers : 1
Total pins : 2 / 475 ( < 1 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )