📄 twice.tan.rpt
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Classic Timing Analyzer report for twice
Mon Dec 22 10:44:19 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. tpd
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------+---------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 6.862 ns ; d_out ; clk_out ; clk ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 5.122 ns ; clk ; clk_out ; -- ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; d_out ; d_out ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-------+---------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; d_out ; d_out ; clk ; clk ; None ; None ; 0.407 ns ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------+---------+------------+
; N/A ; None ; 6.862 ns ; d_out ; clk_out ; clk ;
+-------+--------------+------------+-------+---------+------------+
+--------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+---------+
; N/A ; None ; 5.122 ns ; clk ; clk_out ;
+-------+-------------------+-----------------+------+---------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Mon Dec 22 10:44:17 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off twice -c twice --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "clk_temp~0" as buffer
Info: Detected ripple clock "d_out" as buffer
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "d_out" and destination register "d_out"
Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.407 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'
Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X30_Y35_N0; Fanout = 1; COMB Node = 'd_out~2'
Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'
Info: Total cell delay = 0.407 ns ( 100.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.529 ns
Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.630 ns) + CELL(0.150 ns) = 1.759 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'
Info: 3: + IC(0.233 ns) + CELL(0.537 ns) = 2.529 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'
Info: Total cell delay = 1.666 ns ( 65.88 % )
Info: Total interconnect delay = 0.863 ns ( 34.12 % )
Info: - Longest clock path from clock "clk" to source register is 2.529 ns
Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.630 ns) + CELL(0.150 ns) = 1.759 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'
Info: 3: + IC(0.233 ns) + CELL(0.537 ns) = 2.529 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'
Info: Total cell delay = 1.666 ns ( 65.88 % )
Info: Total interconnect delay = 0.863 ns ( 34.12 % )
Info: + Micro clock to output delay of source is 0.250 ns
Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk" to destination pin "clk_out" through register "d_out" is 6.862 ns
Info: + Longest clock path from clock "clk" to source register is 2.529 ns
Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.630 ns) + CELL(0.150 ns) = 1.759 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'
Info: 3: + IC(0.233 ns) + CELL(0.537 ns) = 2.529 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'
Info: Total cell delay = 1.666 ns ( 65.88 % )
Info: Total interconnect delay = 0.863 ns ( 34.12 % )
Info: + Micro clock to output delay of source is 0.250 ns
Info: + Longest register to pin delay is 4.083 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 2; REG Node = 'd_out'
Info: 2: + IC(0.300 ns) + CELL(0.420 ns) = 0.720 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'
Info: 3: + IC(0.575 ns) + CELL(2.788 ns) = 4.083 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'clk_out'
Info: Total cell delay = 3.208 ns ( 78.57 % )
Info: Total interconnect delay = 0.875 ns ( 21.43 % )
Info: Longest tpd from source pin "clk" to destination pin "clk_out" is 5.122 ns
Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.630 ns) + CELL(0.150 ns) = 1.759 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 2; COMB Node = 'clk_temp~0'
Info: 3: + IC(0.575 ns) + CELL(2.788 ns) = 5.122 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'clk_out'
Info: Total cell delay = 3.917 ns ( 76.47 % )
Info: Total interconnect delay = 1.205 ns ( 23.53 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 125 megabytes
Info: Processing ended: Mon Dec 22 10:44:21 2008
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:01
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