twice_modelsim.xrf

用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真

vendor_name = ModelSim
source_file = 1, D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.vwf
source_file = 1, D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/twice.v
source_file = 1, D:/EDA/altera/80/quartus/Z_my_project_08/twice_freqencey/db/twice.cbx.xml
design_name = twice
instance = comp, \d_out~2 , d_out~2, twice, 1
instance = comp, \clk~I , clk, twice, 1
instance = comp, \clk_temp~0 , clk_temp~0, twice, 1
instance = comp, \clk_out~I , clk_out, twice, 1