twice_v.sdo

用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真

// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP2C35F672C6 Package FBGA672
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "twice")
  (DATE "12/22/2008 10:44:25")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 8.0 Build 215 05/29/2008 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE d_out\~2)
    (DELAY
      (ABSOLUTE
        (IOPATH datac combout (323:323:323) (323:323:323))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE d_out)
    (DELAY
      (ABSOLUTE
        (PORT clk (770:770:770) (770:770:770))
        (PORT datain (84:84:84) (84:84:84))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE clk\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (979:979:979) (979:979:979))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE clk_temp\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (300:300:300) (300:300:300))
        (PORT datad (630:630:630) (630:630:630))
        (IOPATH datab combout (420:420:420) (420:420:420))
        (IOPATH datad combout (150:150:150) (150:150:150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE clk_out\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (575:575:575) (575:575:575))
        (IOPATH datain padio (2788:2788:2788) (2788:2788:2788))
      )
    )
  )
)