twice.vo

用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真

// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 8.0 Build 215 05/29/2008 SJ Full Version"

// DATE "12/22/2008 10:44:25"

// 
// Device: Altera EP2C35F672C6 Package FBGA672
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module twice (
	clk,
	clk_out);
input 	clk;
output 	clk_out;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("twice_v.sdo");
// synopsys translate_on

wire \d_out~2_combout ;
wire \d_out~regout ;
wire \clk~combout ;
wire \clk_temp~0_combout ;


// atom is at LCCOMB_X30_Y35_N0
cycloneii_lcell_comb \d_out~2 (
// Equation(s):
// \d_out~2_combout  = !\d_out~regout 

	.dataa(vcc),
	.datab(vcc),
	.datac(\d_out~regout ),
	.datad(vcc),
	.cin(gnd),
	.combout(\d_out~2_combout ),
	.cout());
// synopsys translate_off
defparam \d_out~2 .lut_mask = 16'h0F0F;
defparam \d_out~2 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X30_Y35_N1
cycloneii_lcell_ff d_out(
	.clk(\clk_temp~0_combout ),
	.datain(\d_out~2_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\d_out~regout ));

// atom is at PIN_C13
cycloneii_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .oe_power_up = "low";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .operation_mode = "input";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCCOMB_X30_Y35_N2
cycloneii_lcell_comb \clk_temp~0 (
// Equation(s):
// \clk_temp~0_combout  = LCELL(\d_out~regout  $ \clk~combout )

	.dataa(vcc),
	.datab(\d_out~regout ),
	.datac(vcc),
	.datad(\clk~combout ),
	.cin(gnd),
	.combout(\clk_temp~0_combout ),
	.cout());
// synopsys translate_off
defparam \clk_temp~0 .lut_mask = 16'h33CC;
defparam \clk_temp~0 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at PIN_B12
cycloneii_io \clk_out~I (
	.datain(\clk_temp~0_combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(clk_out));
// synopsys translate_off
defparam \clk_out~I .input_async_reset = "none";
defparam \clk_out~I .input_power_up = "low";
defparam \clk_out~I .input_register_mode = "none";
defparam \clk_out~I .input_sync_reset = "none";
defparam \clk_out~I .oe_async_reset = "none";
defparam \clk_out~I .oe_power_up = "low";
defparam \clk_out~I .oe_register_mode = "none";
defparam \clk_out~I .oe_sync_reset = "none";
defparam \clk_out~I .operation_mode = "output";
defparam \clk_out~I .output_async_reset = "none";
defparam \clk_out~I .output_power_up = "low";
defparam \clk_out~I .output_register_mode = "none";
defparam \clk_out~I .output_sync_reset = "none";
// synopsys translate_on

endmodule