📄 st2fsm.vhd
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--This VHDL code and all associated documentation, comments or other information
--(collectively "VHDL CODE") is provided "AS IS" without warranty of any kind. MICRON
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--Because some jurisdictions prohibit the exclusion or limitation of liability for
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--Copyright 2005 Micron Technology, Inc. All rights reserved.
--------------------------------------------------------------------------------------------
---------------------------------------------------
-- FSM begins
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FSM_MNvcS2 is
generic(
nandBUSwidth: natural := 8;
ErrorFetchCommand: std_logic_vector(7 downto 0) := x"23"
);
port(
-- Debug signals
DebugCURaddreg: out std_logic;
DebugInternalCNT: out std_logic_vector(23 downto 0);
-- Standard synchronous inputs
clk : in std_logic;
Reset_L : in std_logic;
-- STANDARD SRAM interface
ADDR : in std_logic_vector(11 downto 0);
ST2outDATA : out std_logic_vector(7 downto 0);
ST2inDATA : in std_logic_vector(7 downto 0);
CE_L : in std_logic;
WE_L : in std_logic;
OE_L : in std_logic;
INT : out std_logic;
RB_L : out std_logic;
-- NAND or NAND ecc module interface
nandCE_L : out std_logic;
nandCLE_H : out std_logic;
nandALE_H : out std_logic;
nandWE_L : out std_logic;
nandRE_L : out std_logic;
nandWP_L : out std_logic;
nandPRE : out std_logic;
nandDATA : inout std_logic_vector(7 downto 0);
nandRB_L : in std_logic;
errINT : in std_logic;
-- Control signals
-- REGfile signals
--WE_regfile_H: out std_logic;
--REGnum: out std_logic_vector(3 downto 0);
--REGfile_DATA: out std_logic_vector(7 downto 0);
--REGfile_DATAout: in std_logic_vector(7 downto 0);
-- BUFFER1 signals
WE_buffer1_H: out std_logic;
buffer1_ADDR: out std_logic_vector(11 downto 0);
buffer1_DATA: out std_logic_vector(7 downto 0);
buffer1_DATAout: in std_logic_vector(7 downto 0);
-- BUFFER2 signals
WE_buffer2_H: out std_logic;
buffer2_ADDR: out std_logic_vector(11 downto 0);
buffer2_DATA: out std_logic_vector(7 downto 0);
buffer2_DATAout: in std_logic_vector(7 downto 0);
-- disabling ECC module signal
enableECCmodule: out std_logic
);
end FSM_MNvcS2;
architecture syn of FSM_MNvcS2 is
type state is (Start, enableTOG0, STreadstatusCMD, STreadstatusREAD, STreadID, STreadIDadd00,
STreadIDfourReads, STeraseblock, STeraseblockADDcycles, STeraseblockCMDd0,
STresetNAND, STreadpage, STreadpageADDlatch00, STreadpageADDlatch3cycles,
STreadpageCMDfinal30h, STreadpageREADS, STreadpageSWAPbuf, STwaitforRB0,
STwaitforRB1, STprogrampage, STprogrampageADDlatch00, STprogrampageADDlatch3cycles,
STprogrampageWRITES, STprogrampageCMDfinal10h, STprogrampageCHbuf,
STprogrampageSWstatusRB, STfetchERRORs, STfetchERRORseightReads, STreadpageCORwaitforRB,
STreadpageCORRECT, STreadpageCORRECTaddr);
type command is (ReadID, pageREAD, programPAGE, ReadSTATUS, erasepage, resetnand);
-- state signals for state machine
signal Cstate : state;
signal Nstate : state;
signal NEXTtonextST, NEXTtonextST2: state;
signal internal_nandDATA: std_logic_vector(nandBUSwidth - 1 downto 0);
-- FSM mux select signals
signal buffer1_nandDATA_in, buffer2_nandDATA_in, nandDATA_from_buffer1, nandDATA_from_buffer2, nandDATA_fsm : std_logic;
signal outputVEC1, outputVEC2: std_logic_vector(4 downto 0);
-- Repetition counter signals
signal internalCNT, CNTupto, internalCNTaddr: std_logic_vector(11 downto 0);
signal internalCNTRst_L, incintCNT, OnedelayedINCcnt : std_logic;
-- Toggle state machine stuff
signal enableTOGGLE, doneTOGGLE: std_logic;
type TOGstate is (toggleWAIT, toggle1, toggle2, toggleDONE);
signal cTOGstate: TOGstate;
signal delayCNT: std_logic_vector(2 downto 0);
signal incDcnt, rstDcnt_L: std_logic;
signal nTOGstate: TOGstate;
-- System attributes i.e. Register FILE registers
signal Device8_not16, ECCpresent, buffer1or2: std_logic;
signal Device_Size:std_logic_vector(1 downto 0);
signal CommandREG, StatusREG: std_logic_vector(7 downto 0);
-- Error location array
type errorLOCtype is array (7 downto 0) of std_logic_vector(7 downto 0);
signal errorLOC: errorLOCtype;
type nandIDtype is array (3 downto 0) of std_logic_vector(7 downto 0);
type regADDRtype is array (2 downto 0) of std_logic_vector(7 downto 0);
type DOUBLEregADDRtype is array (1 downto 0) of regADDRtype;
signal nandID: nandIDtype;
signal REGaddress: DOUBLEregADDRtype;
signal currentADDreg, flipTHEt: std_logic;
signal DEBUGstatevector: std_logic_vector(7 downto 0);
signal nandRB_Lreg1, nandRB_Lfinal: std_logic;
--signal ADDressaddr: std_logic_vector(1 downto 0);
-- signals for error correction
signal errCORaddrIN, corWE: std_logic;
signal corINPUTdata: std_logic_vector(7 downto 0);
signal corADDR: std_logic_vector(11 downto 0);
-- Constants based on control registers
signal bytesCONTROLLED: std_logic_vector(11 downto 0);
begin
punchOUTconstants: process(ECCpresent)
begin
if(ECCpresent = '0') then
bytesCONTROLLED <= x"840";
else
bytesCONTROLLED <= x"834";
end if;
end process punchOUTconstants;
doublebufnandRB_L:process(clk)
begin
if(rising_edge(clk)) then
nandRB_Lreg1 <= nandRB_L;
nandRB_Lfinal <= nandRB_Lreg1;
end if;
end process;
DebugCURaddreg <= OneDelayedINCcnt;
--DebugInternalCNT <= internalCNTaddr; --DebugInternalCNT <= "0000" & DEBUGstatevector;
--DebugInternalCNT <= buffer1or2 & nandDATA_fsm & nandDATA_from_buffer2 & nandDATA_from_buffer1 & DEBUGstatevector;
--DebugInternalCNT <= delayCNT & nandDATA_from_buffer1 & DEBUGstatevector;
DebugInternalCNT <= corADDR & corWE & errCORaddrIN & errINT & nandRB_L & DEBUGstatevector;
TflipFLOPprocess:process(clk, Reset_L, flipTHEt, currentADDreg)
begin
if(rising_edge(clk)) then
if(reset_L = '0') then
currentADDreg <= '0';
else
if(flipTHEt = '1') then
currentADDreg <= not(currentADDreg);
end if;
end if;
end if;
end process TflipFLOPprocess;
enableECCmodule <= ECCpresent;
statemachine: process(clk, Reset_L, cSTATE, nandRB_Lfinal, buffer1or2, buffer2_DATAout, buffer1_DATAout)
variable nandaddress1, nandaddress2, nandaddress3: std_logic_vector(7 downto 0);
-- Format
-- bit 0 - CE_L
-- bit 1 - CLE_H
-- bit 2 - ALE_H
-- bit 3 - WE_L
-- bit 4 - RE_L
variable currentCMD: command;
variable VARcorINPUTdata: std_logic_vector(7 downto 0);
variable outputFROMbuf: std_logic_vector(7 downto 0);
begin
if (buffer1or2 = '0') then
outputFROMbuf := buffer2_DATAout;
else
outputFROMbuf := buffer1_DATAout;
end if;
case errorLOC(conv_integer(internalCNT(1 downto 0) & '0'))(2 downto 0) is
when "000" =>
VARcorINPUTdata := outputFROMbuf(7 downto 1) & not(outputFROMbuf(0));
when "001" =>
VARcorINPUTdata := outputFROMbuf(7 downto 2) & not(outputFROMbuf(1)) & outputFROMbuf(0);
when "010" =>
VARcorINPUTdata := outputFROMbuf(7 downto 3) & not(outputFROMbuf(2)) & outputFROMbuf(1 downto 0);
when "011" =>
VARcorINPUTdata := outputFROMbuf(7 downto 4) & not(outputFROMbuf(3)) & outputFROMbuf(2 downto 0);
when "100" =>
VARcorINPUTdata := outputFROMbuf(7 downto 5) & not(outputFROMbuf(4)) & outputFROMbuf(3 downto 0);
when "101" =>
VARcorINPUTdata := outputFROMbuf(7 downto 6) & not(outputFROMbuf(5)) & outputFROMbuf(4 downto 0);
when "110" =>
VARcorINPUTdata := outputFROMbuf(7) & not(outputFROMbuf(6)) & outputFROMbuf(5 downto 0);
when "111" =>
VARcorINPUTdata := not(outputFROMbuf(7)) & outputFROMbuf(6 downto 0);
when others =>
VARcorINPUTdata := outputFROMbuf;
end case;
if(rising_edge(clk)) then
if(Reset_L = '0') then
Cstate <= Start;
NEXTtonextST <= Start;
CNTupto <= x"000";
internalCNTaddr <= x"000";
-- New REGfile handling
nandID <= (x"00", x"00", x"00", x"00");
REGaddress <= ((x"00", x"00", x"00"), (x"00", x"00", x"00"));
errorLOC <= (x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00");
Device8_not16 <= '0';
ECCpresent <= '0';
buffer1or2 <= '0';
Device_Size <= "00";
CommandREG <= x"00";
nandPRE <= '1';
else
nandPRE <= '1';
if(ADDR = x"FF4" and WE_L = '0' and CE_L = '0') then
REGaddress(conv_integer(currentADDreg))(0) <= ST2inDATA;
elsif(ADDR = x"FF5" and WE_L = '0' and CE_L = '0') then
REGaddress(conv_integer(currentADDreg))(1) <= ST2inDATA;
elsif(ADDR = x"FF6" and WE_L = '0' and CE_L = '0') then
REGaddress(conv_integer(currentADDreg))(2) <= ST2inDATA;
elsif(ADDR = x"FF7" and WE_L = '0' and CE_L = '0') then
Device8_not16 <= ST2inDATA(0);
Device_Size <= ST2inDATA(2 downto 1);
ECCpresent <= ST2inDATA(6);
elsif(ADDR = x"FF8" and WE_L = '0' and CE_L = '0') then
buffer1or2 <= ST2inDATA(0);
elsif(ADDR = x"FFA" and WE_L = '0' and CE_L = '0') then
CommandREG <= ST2inDATA;
end if;
internalCNTaddr <= internalCNT;
case cSTATE is
when Start =>
NEXTtonextST <= Start;
cntUPTO <= x"000";
NEXTtonextST2 <= Start;
-- Multiple Use states
when enableTOG0 =>
cntUPTO <= x"000";
when STwaitforRB0 =>
cntUPTO <= x"000";
when STwaitforRB1 =>
cntUPTO <= x"000";
-- Program cycles
when STprogrampageCHbuf =>
StatusREG(5) <= '0';
if(CommandREG(0) = '1') then
buffer1or2 <= not(CommandREG(1));
else
buffer1or2 <= not(buffer1or2);
end if;
NEXTtonextST <= STprogrampage;
when STprogrampage =>
NEXTtonextST <= STprogrampageADDlatch00;
when STprogrampageADDlatch00 =>
cntUPTO <= x"002";
NEXTtonextST <= STprogrampageADDlatch3cycles;
when STprogrampageADDlatch3cycles =>
cntUPTO <= x"003";
NEXTtonextST <= STprogrampageWRITES;
when STprogrampageWRITES =>
NEXTtonextST <= STprogrampageCMDfinal10h;
--cntUPTO <= x"834";
cntUPTO <= bytesCONTROLLED;
when STprogrampageCMDfinal10h =>
NEXTtonextST <= STprogrampageSWstatusRB;
when STprogrampageSWstatusRB =>
StatusREG(5) <= '1';
cntUPTO <= x"000";
NEXTtonextST <= Start;
-- Read cycles
when STreadpage =>
StatusREG(5) <= '0';
if(CommandREG(0) = '1') then
-- shift control to the buffer which is free
-- that is not the one in the command
buffer1or2 <= not(CommandREG(1));
end if;
NEXTtonextST <= STreadpageADDlatch00;
when STreadpageADDlatch00 =>
cntUPTO <= x"002";
NEXTtonextST <= STreadpageADDlatch3cycles;
when STreadpageADDlatch3cycles =>
cntUPTO <= x"003";
NEXTtonextST <= STreadpageCMDfinal30h;
when STreadpageCMDfinal30h =>
NEXTtonextST <= STreadpageREADS;
when STreadpageREADS =>
NEXTtonextST <= Start;
cntUPTO <= bytesCONTROLLED;
--cntUPTO <= x"834";
when STreadpageSWAPbuf =>
StatusREG(5) <= '1';
cntUPTO <= x"000";
buffer1or2 <= not(buffer1or2);
when STreadpageCORwaitforRB =>
NEXTtonextST2 <= STreadpageCORRECTaddr;
when STreadpageCORRECT =>
NEXTtonextST2 <= STreadpageCORRECTaddr;
when STreadpageCORRECTaddr =>
if (delayCNT = "001") then
corINPUTdata <= VARcorINPUTdata;
end if;
cntUPTO <= x"004";
-- Erase cycles
when STeraseblock =>
StatusREG(5) <= '0';
--internal_nandDATA <= x"60";
NEXTtonextST <= STeraseblockADDcycles;
when STeraseblockADDcycles =>
--internal_nandDATA <= REGfile_DATAout;
cntUPTO <= x"003";
NEXTtonextST <= STeraseblockCMDd0;
when STeraseblockCMDd0 =>
NEXTtonextST <= STprogrampageSWstatusRB;
--internal_nandDATA <= x"D0";
cntUPTO <= x"000";
-- Reset cycles
when STresetNAND =>
--internal_nandDATA <= x"FF";
NEXTtonextST <= Start;
cntUPTO <= x"000";
-- Fetch Error cycles
when STfetchERRORs =>
--internal_nandDATA <= x"90";
cntUPTO <= x"000";
NEXTtonextST <= STfetchERRORseightReads;
when STfetchERRORseightReads =>
if(incintCNT = '1') then
errorLOC(conv_integer(internalCNT(2 downto 0))) <= nandDATA;
end if;
cntUPTO <= x"008";
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