prev_cmp_cursor.tan.qmsg

针对FPGA

{ "Info" "ITDB_TH_RESULT" "LEDG\[1\]~reg0 KEY\[1\] CLOCK_50 -3.264 ns register " "Info: th for register \"LEDG\[1\]~reg0\" (data pin = \"KEY\[1\]\", clock pin = \"CLOCK_50\") is -3.264 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.684 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.684 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.537 ns) 2.684 ns LEDG\[1\]~reg0 3 REG LCFF_X49_Y20_N21 1 " "Info: 3: + IC(1.030 ns) + CELL(0.537 ns) = 2.684 ns; Loc. = LCFF_X49_Y20_N21; Fanout = 1; REG Node = 'LEDG\[1\]~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { CLOCK_50~clkctrl LEDG[1]~reg0 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.23 % ) " "Info: Total cell delay = 1.536 ns ( 57.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.148 ns ( 42.77 % ) " "Info: Total interconnect delay = 1.148 ns ( 42.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.684 ns" { CLOCK_50 CLOCK_50~clkctrl LEDG[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.684 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LEDG[1]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.030ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.214 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.214 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns KEY\[1\] 1 PIN PIN_N23 4 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_N23; Fanout = 4; PIN Node = 'KEY\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.138 ns) + CELL(0.150 ns) 6.130 ns LEDG\[1\]~22 2 COMB LCCOMB_X49_Y20_N20 1 " "Info: 2: + IC(5.138 ns) + CELL(0.150 ns) = 6.130 ns; Loc. = LCCOMB_X49_Y20_N20; Fanout = 1; COMB Node = 'LEDG\[1\]~22'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.288 ns" { KEY[1] LEDG[1]~22 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.214 ns LEDG\[1\]~reg0 3 REG LCFF_X49_Y20_N21 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.214 ns; Loc. = LCFF_X49_Y20_N21; Fanout = 1; REG Node = 'LEDG\[1\]~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { LEDG[1]~22 LEDG[1]~reg0 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.076 ns ( 17.32 % ) " "Info: Total cell delay = 1.076 ns ( 17.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.138 ns ( 82.68 % ) " "Info: Total interconnect delay = 5.138 ns ( 82.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.214 ns" { KEY[1] LEDG[1]~22 LEDG[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.214 ns" { KEY[1] {} KEY[1]~combout {} LEDG[1]~22 {} LEDG[1]~reg0 {} } { 0.000ns 0.000ns 5.138ns 0.000ns } { 0.000ns 0.842ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.684 ns" { CLOCK_50 CLOCK_50~clkctrl LEDG[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.684 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LEDG[1]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.030ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.214 ns" { KEY[1] LEDG[1]~22 LEDG[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.214 ns" { KEY[1] {} KEY[1]~combout {} LEDG[1]~22 {} LEDG[1]~reg0 {} } { 0.000ns 0.000ns 5.138ns 0.000ns } { 0.000ns 0.842ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "117 " "Info: Allocated 117 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 16 17:20:56 2008 " "Info: Processing ended: Wed Jul 16 17:20:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}