📄 prev_cmp_cursor.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register X\[0\] register B_Val\[0\] 197.51 MHz 5.063 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 197.51 MHz between source register \"X\[0\]\" and destination register \"B_Val\[0\]\" (period= 5.063 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.850 ns + Longest register register " "Info: + Longest register to register delay is 4.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns X\[0\] 1 REG LCFF_X48_Y23_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X48_Y23_N1; Fanout = 5; REG Node = 'X\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { X[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.393 ns) 0.707 ns Add0~133 2 COMB LCCOMB_X48_Y23_N4 2 " "Info: 2: + IC(0.314 ns) + CELL(0.393 ns) = 0.707 ns; Loc. = LCCOMB_X48_Y23_N4; Fanout = 2; COMB Node = 'Add0~133'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.707 ns" { X[0] Add0~133 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.778 ns Add0~135 3 COMB LCCOMB_X48_Y23_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.778 ns; Loc. = LCCOMB_X48_Y23_N6; Fanout = 2; COMB Node = 'Add0~135'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~133 Add0~135 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.849 ns Add0~137 4 COMB LCCOMB_X48_Y23_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.849 ns; Loc. = LCCOMB_X48_Y23_N8; Fanout = 2; COMB Node = 'Add0~137'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~135 Add0~137 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.920 ns Add0~139 5 COMB LCCOMB_X48_Y23_N10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 0.920 ns; Loc. = LCCOMB_X48_Y23_N10; Fanout = 2; COMB Node = 'Add0~139'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~137 Add0~139 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.991 ns Add0~141 6 COMB LCCOMB_X48_Y23_N12 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 0.991 ns; Loc. = LCCOMB_X48_Y23_N12; Fanout = 2; COMB Node = 'Add0~141'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~139 Add0~141 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.150 ns Add0~143 7 COMB LCCOMB_X48_Y23_N14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.159 ns) = 1.150 ns; Loc. = LCCOMB_X48_Y23_N14; Fanout = 2; COMB Node = 'Add0~143'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~141 Add0~143 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.221 ns Add0~145 8 COMB LCCOMB_X48_Y23_N16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.221 ns; Loc. = LCCOMB_X48_Y23_N16; Fanout = 2; COMB Node = 'Add0~145'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~143 Add0~145 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.631 ns Add0~146 9 COMB LCCOMB_X48_Y23_N18 3 " "Info: 9: + IC(0.000 ns) + CELL(0.410 ns) = 1.631 ns; Loc. = LCCOMB_X48_Y23_N18; Fanout = 3; COMB Node = 'Add0~146'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add0~145 Add0~146 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.393 ns) 2.473 ns Add1~103 10 COMB LCCOMB_X49_Y23_N8 2 " "Info: 10: + IC(0.449 ns) + CELL(0.393 ns) = 2.473 ns; Loc. = LCCOMB_X49_Y23_N8; Fanout = 2; COMB Node = 'Add1~103'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.842 ns" { Add0~146 Add1~103 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.883 ns Add1~104 11 COMB LCCOMB_X49_Y23_N10 1 " "Info: 11: + IC(0.000 ns) + CELL(0.410 ns) = 2.883 ns; Loc. = LCCOMB_X49_Y23_N10; Fanout = 1; COMB Node = 'Add1~104'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add1~103 Add1~104 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(0.414 ns) 3.763 ns LessThan1~174 12 COMB LCCOMB_X50_Y23_N22 1 " "Info: 12: + IC(0.466 ns) + CELL(0.414 ns) = 3.763 ns; Loc. = LCCOMB_X50_Y23_N22; Fanout = 1; COMB Node = 'LessThan1~174'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.880 ns" { Add1~104 LessThan1~174 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 4.173 ns LessThan1~175 13 COMB LCCOMB_X50_Y23_N24 1 " "Info: 13: + IC(0.000 ns) + CELL(0.410 ns) = 4.173 ns; Loc. = LCCOMB_X50_Y23_N24; Fanout = 1; COMB Node = 'LessThan1~175'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { LessThan1~174 LessThan1~175 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.150 ns) 4.766 ns always0~195 14 COMB LCCOMB_X49_Y23_N28 1 " "Info: 14: + IC(0.443 ns) + CELL(0.150 ns) = 4.766 ns; Loc. = LCCOMB_X49_Y23_N28; Fanout = 1; COMB Node = 'always0~195'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.593 ns" { LessThan1~175 always0~195 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.850 ns B_Val\[0\] 15 REG LCFF_X49_Y23_N29 30 " "Info: 15: + IC(0.000 ns) + CELL(0.084 ns) = 4.850 ns; Loc. = LCFF_X49_Y23_N29; Fanout = 30; REG Node = 'B_Val\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { always0~195 B_Val[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.178 ns ( 65.53 % ) " "Info: Total cell delay = 3.178 ns ( 65.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.672 ns ( 34.47 % ) " "Info: Total interconnect delay = 1.672 ns ( 34.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.850 ns" { X[0] Add0~133 Add0~135 Add0~137 Add0~139 Add0~141 Add0~143 Add0~145 Add0~146 Add1~103 Add1~104 LessThan1~174 LessThan1~175 always0~195 B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.850 ns" { X[0] {} Add0~133 {} Add0~135 {} Add0~137 {} Add0~139 {} Add0~141 {} Add0~143 {} Add0~145 {} Add0~146 {} Add1~103 {} Add1~104 {} LessThan1~174 {} LessThan1~175 {} always0~195 {} B_Val[0] {} } { 0.000ns 0.314ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.449ns 0.000ns 0.466ns 0.000ns 0.443ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.410ns 0.393ns 0.410ns 0.414ns 0.410ns 0.150ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.675 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.675 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'CLOCK_50~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.537 ns) 2.675 ns B_Val\[0\] 3 REG LCFF_X49_Y23_N29 30 " "Info: 3: + IC(1.021 ns) + CELL(0.537 ns) = 2.675 ns; Loc. = LCFF_X49_Y23_N29; Fanout = 30; REG Node = 'B_Val\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.558 ns" { CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.42 % ) " "Info: Total cell delay = 1.536 ns ( 57.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.139 ns ( 42.58 % ) " "Info: Total interconnect delay = 1.139 ns ( 42.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.675 ns" { CLOCK_50 CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.675 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} B_Val[0] {} } { 0.000ns 0.000ns 0.118ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.674 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'CLOCK_50~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.537 ns) 2.674 ns X\[0\] 3 REG LCFF_X48_Y23_N1 5 " "Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X48_Y23_N1; Fanout = 5; REG Node = 'X\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.557 ns" { CLOCK_50~clkctrl X[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.44 % ) " "Info: Total cell delay = 1.536 ns ( 57.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.138 ns ( 42.56 % ) " "Info: Total interconnect delay = 1.138 ns ( 42.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { CLOCK_50 CLOCK_50~clkctrl X[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.674 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} X[0] {} } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.675 ns" { CLOCK_50 CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.675 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} B_Val[0] {} } { 0.000ns 0.000ns 0.118ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { CLOCK_50 CLOCK_50~clkctrl X[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.674 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} X[0] {} } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.850 ns" { X[0] Add0~133 Add0~135 Add0~137 Add0~139 Add0~141 Add0~143 Add0~145 Add0~146 Add1~103 Add1~104 LessThan1~174 LessThan1~175 always0~195 B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.850 ns" { X[0] {} Add0~133 {} Add0~135 {} Add0~137 {} Add0~139 {} Add0~141 {} Add0~143 {} Add0~145 {} Add0~146 {} Add1~103 {} Add1~104 {} LessThan1~174 {} LessThan1~175 {} always0~195 {} B_Val[0] {} } { 0.000ns 0.314ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.449ns 0.000ns 0.466ns 0.000ns 0.443ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.410ns 0.393ns 0.410ns 0.414ns 0.410ns 0.150ns 0.084ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.675 ns" { CLOCK_50 CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.675 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} B_Val[0] {} } { 0.000ns 0.000ns 0.118ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { CLOCK_50 CLOCK_50~clkctrl X[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.674 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} X[0] {} } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "X\[5\] KEY\[0\] CLOCK_50 6.419 ns register " "Info: tsu for register \"X\[5\]\" (data pin = \"KEY\[0\]\", clock pin = \"CLOCK_50\") is 6.419 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.128 ns + Longest pin register " "Info: + Longest pin to register delay is 9.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns KEY\[0\] 1 PIN PIN_G26 54 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 54; PIN Node = 'KEY\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.611 ns) + CELL(0.150 ns) 6.623 ns X\[7\]~1186 2 COMB LCCOMB_X48_Y22_N26 2 " "Info: 2: + IC(5.611 ns) + CELL(0.150 ns) = 6.623 ns; Loc. = LCCOMB_X48_Y22_N26; Fanout = 2; COMB Node = 'X\[7\]~1186'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.761 ns" { KEY[0] X[7]~1186 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.415 ns) 7.297 ns X\[7\]~1188 3 COMB LCCOMB_X48_Y22_N20 1 " "Info: 3: + IC(0.259 ns) + CELL(0.415 ns) = 7.297 ns; Loc. = LCCOMB_X48_Y22_N20; Fanout = 1; COMB Node = 'X\[7\]~1188'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.674 ns" { X[7]~1186 X[7]~1188 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.275 ns) 7.829 ns X\[7\]~1189 4 COMB LCCOMB_X48_Y22_N30 10 " "Info: 4: + IC(0.257 ns) + CELL(0.275 ns) = 7.829 ns; Loc. = LCCOMB_X48_Y22_N30; Fanout = 10; COMB Node = 'X\[7\]~1189'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.532 ns" { X[7]~1188 X[7]~1189 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.795 ns) + CELL(0.420 ns) 9.044 ns Add5~1122 5 COMB LCCOMB_X47_Y23_N18 1 " "Info: 5: + IC(0.795 ns) + CELL(0.420 ns) = 9.044 ns; Loc. = LCCOMB_X47_Y23_N18; Fanout = 1; COMB Node = 'Add5~1122'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { X[7]~1189 Add5~1122 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 90 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 9.128 ns X\[5\] 6 REG LCFF_X47_Y23_N19 6 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 9.128 ns; Loc. = LCFF_X47_Y23_N19; Fanout = 6; REG Node = 'X\[5\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Add5~1122 X[5] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.206 ns ( 24.17 % ) " "Info: Total cell delay = 2.206 ns ( 24.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.922 ns ( 75.83 % ) " "Info: Total interconnect delay = 6.922 ns ( 75.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.128 ns" { KEY[0] X[7]~1186 X[7]~1188 X[7]~1189 Add5~1122 X[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.128 ns" { KEY[0] {} KEY[0]~combout {} X[7]~1186 {} X[7]~1188 {} X[7]~1189 {} Add5~1122 {} X[5] {} } { 0.000ns 0.000ns 5.611ns 0.259ns 0.257ns 0.795ns 0.000ns } { 0.000ns 0.862ns 0.150ns 0.415ns 0.275ns 0.420ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.673 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'CLOCK_50~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.019 ns) + CELL(0.537 ns) 2.673 ns X\[5\] 3 REG LCFF_X47_Y23_N19 6 " "Info: 3: + IC(1.019 ns) + CELL(0.537 ns) = 2.673 ns; Loc. = LCFF_X47_Y23_N19; Fanout = 6; REG Node = 'X\[5\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { CLOCK_50~clkctrl X[5] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.46 % ) " "Info: Total cell delay = 1.536 ns ( 57.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.137 ns ( 42.54 % ) " "Info: Total interconnect delay = 1.137 ns ( 42.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.673 ns" { CLOCK_50 CLOCK_50~clkctrl X[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.673 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} X[5] {} } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.128 ns" { KEY[0] X[7]~1186 X[7]~1188 X[7]~1189 Add5~1122 X[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.128 ns" { KEY[0] {} KEY[0]~combout {} X[7]~1186 {} X[7]~1188 {} X[7]~1189 {} Add5~1122 {} X[5] {} } { 0.000ns 0.000ns 5.611ns 0.259ns 0.257ns 0.795ns 0.000ns } { 0.000ns 0.862ns 0.150ns 0.415ns 0.275ns 0.420ns 0.084ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.673 ns" { CLOCK_50 CLOCK_50~clkctrl X[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.673 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} X[5] {} } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 VGA_G\[5\] B_Val\[0\] 9.776 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"VGA_G\[5\]\" through register \"B_Val\[0\]\" is 9.776 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.675 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 2.675 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'CLOCK_50~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.537 ns) 2.675 ns B_Val\[0\] 3 REG LCFF_X49_Y23_N29 30 " "Info: 3: + IC(1.021 ns) + CELL(0.537 ns) = 2.675 ns; Loc. = LCFF_X49_Y23_N29; Fanout = 30; REG Node = 'B_Val\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.558 ns" { CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.42 % ) " "Info: Total cell delay = 1.536 ns ( 57.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.139 ns ( 42.58 % ) " "Info: Total interconnect delay = 1.139 ns ( 42.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.675 ns" { CLOCK_50 CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.675 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} B_Val[0] {} } { 0.000ns 0.000ns 0.118ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.851 ns + Longest register pin " "Info: + Longest register to pin delay is 6.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns B_Val\[0\] 1 REG LCFF_X49_Y23_N29 30 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X49_Y23_N29; Fanout = 30; REG Node = 'B_Val\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { B_Val[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.053 ns) + CELL(2.798 ns) 6.851 ns VGA_G\[5\] 2 PIN PIN_A10 0 " "Info: 2: + IC(4.053 ns) + CELL(2.798 ns) = 6.851 ns; Loc. = PIN_A10; Fanout = 0; PIN Node = 'VGA_G\[5\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.851 ns" { B_Val[0] VGA_G[5] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 40.84 % ) " "Info: Total cell delay = 2.798 ns ( 40.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.053 ns ( 59.16 % ) " "Info: Total interconnect delay = 4.053 ns ( 59.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.851 ns" { B_Val[0] VGA_G[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.851 ns" { B_Val[0] {} VGA_G[5] {} } { 0.000ns 4.053ns } { 0.000ns 2.798ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.675 ns" { CLOCK_50 CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.675 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} B_Val[0] {} } { 0.000ns 0.000ns 0.118ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.851 ns" { B_Val[0] VGA_G[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.851 ns" { B_Val[0] {} VGA_G[5] {} } { 0.000ns 4.053ns } { 0.000ns 2.798ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CLOCK_50 VGA_CLK 5.541 ns Longest " "Info: Longest tpd from source pin \"CLOCK_50\" to destination pin \"VGA_CLK\" is 5.541 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.744 ns) + CELL(2.798 ns) 5.541 ns VGA_CLK 2 PIN PIN_B8 0 " "Info: 2: + IC(1.744 ns) + CELL(2.798 ns) = 5.541 ns; Loc. = PIN_B8; Fanout = 0; PIN Node = 'VGA_CLK'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.542 ns" { CLOCK_50 VGA_CLK } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.797 ns ( 68.53 % ) " "Info: Total cell delay = 3.797 ns ( 68.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.744 ns ( 31.47 % ) " "Info: Total interconnect delay = 1.744 ns ( 31.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.541 ns" { CLOCK_50 VGA_CLK } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.541 ns" { CLOCK_50 {} CLOCK_50~combout {} VGA_CLK {} } { 0.000ns 0.000ns 1.744ns } { 0.000ns 0.999ns 2.798ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
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