product.cfg

flash programming STI 5.5.1.4 DCU3

################################################################################
## vi:sw=3 ts=3:et:
## 
## File: $RCSfile: product.cfg,v $
##       $Revision: 1.47 $
##       $Date: 2003/06/20 16:05:06 $
##            
## Copyright [2000] Pace Micro Technology PLC.   All rights reserved.
## 
## The copyright in this material is owned by Pace Micro Technology PLC
## ("Pace"). This material is regarded as a highly confidential trade secret of
## Pace. It may not be reproduced, used, sold or in any other way exploited or
## transferred to any third party without the prior written permission of Pace.
## 
################################################################################

## include reset_dcu.cfg  not in DCU R1_9_5 toolset
include board.cfg
include targets.cfg
include cpustall.cfg
include ir.cfg
include hddi.cfg

###########################################################################################################
########## MEMORY AND SECTION PLACEMENT PROCEDURES ########################################################
###########################################################################################################


## place_cmd_hostboot ##
proc place_cmd_hostboot {
 
##  memory EMI0_RESERVED  (addressof -q EMI0_SDRAM) (sizeof -q EMI0_SDRAM) RESERVED
##  memory FLASH_RESERVED (addressof -q FLASH)      (sizeof -q FLASH)      RESERVED
##  memory BOOT_RESERVED  (addressof -q BOOT)       (sizeof -q BOOT)       RESERVED
                                                                         
  define cfg_romboot_addr (CONFIG_ADDR - 2)

##  write MAIN Rom Boot Address is -x (CONFIG_ADDR - 2)

  PlaceDebugTrapHandler INTERNAL

  heap  INTERNAL
  stack INTERNAL
}
## end  place_cmd_hostboot ##

## place_cmd_romboot ##
proc place_cmd_romboot {
 
##  memory EMI0_RESERVED  (addressof -q EMI0_SDRAM) (sizeof -q EMI0_SDRAM) RESERVED
##  memory FLASH_RESERVED (addressof -q FLASH)      (sizeof -q FLASH)      RESERVED
##  memory BOOT_RESERVED  (addressof -q BOOT)       (sizeof -q BOOT)       RESERVED
                                                                         
  define cfg_romboot_addr (CONFIG_ADDR - 2)

  write MAIN Rom Boot Address is -x (CONFIG_ADDR - 2)

  place <startup_section>  BOOT
  place <shutdown_section> BOOT

  PlaceDebugTrapHandler INTERNAL
  
  bootiptr ((CONFIG_ADDR+CONFIG_SIZE)-2 ) 

  heap  INTERNAL
  stack INTERNAL
}
## end  place_cmd_romboot ##

## place_cmd_striped_romboot ##
proc place_cmd_striped_romboot {
 
##  memory EMI0_RESERVED  (addressof -q EMI0_SDRAM) (sizeof -q EMI0_SDRAM) RESERVED
##  memory FLASH_RESERVED (addressof -q FLASH)      (sizeof -q FLASH)      RESERVED
##  memory BOOT_RESERVED  (addressof -q BOOT)       (sizeof -q BOOT)       RESERVED
                                                                         
  define cfg_romboot_addr ((FLASH_MIRROR_ADDR+FLASH_BANK_SIZE)-CONFIG_SIZE - 2)

  write MAIN Rom Boot Address is -x ((FLASH_MIRROR_ADDR+FLASH_BANK_SIZE)-CONFIG_SIZE - 2)
  write LOADER Rom Boot Address is -x ((FLASH_MIRROR_ADDR+FLASH_BANK_SIZE) - 2)

  place <startup_section>  BOOT
  place <shutdown_section> BOOT

  PlaceDebugTrapHandler INTERNAL

  place <tanto_fpga_code_const> EXTENDED_BOOT
  
  bootiptr ((CONFIG_ADDR+CONFIG_SIZE)-2 ) 

  heap  INTERNAL
  stack INTERNAL
}
## end  place_cmd_striped_romboot ##

###########################################
## place_cmd_main_general ##

proc place_cmd_main_general {
    
  ## create some symbols whose values contain the start addresses and sizes of
  ## EMI0 SDRAMs. 

  cfg_emi0_start = (addressof -q EMI0_SDRAM)
  cfg_emi0_size  = (sizeof -q EMI0_SDRAM)

  ## The whole of the internal memory is available to the drivers
  ## for general data placement
  driver_internal_start  = (addressof -q INTERNAL)
  driver_internal_size   = (sizeof -q INTERNAL) 


  ## The bottom 8M of EMI SDRAM is cacheable

  ## Bottom 1.8M of EMI SDRAM is for the cacheable heap 
  ## This will be used by OS_DymanicMalloc
  cached_heap_start = cfg_emi0_start
  cached_heap_size  = ( 1800*K ) 

  ## Next 6.5M is cacheable 
  cached_start      = cached_heap_start + cached_heap_size 
  cached_size       = ( 8*M ) - cached_heap_size

  ## Define the rest of EMI as the non cacheable data area
  ## Note - the Instruction cache is still enabled in this area
  non_cached_start  = cfg_emi0_start + cached_heap_size + cached_size
  non_cached_size   = cfg_emi0_size  - cached_heap_size - cached_size


  ## Define memory segments 
  memory  NON_CACHED_RAM     (non_cached_start)      (non_cached_size)        RAM
  memory  CACHED_HEAP        (cached_heap_start)     (cached_heap_size)       RAM
  memory  CACHED_RAM         (cached_start)          (cached_size )           RAM
  memory  DRIVER_INTERNAL    (driver_internal_start) (driver_internal_size)   RAM

  ## Default data placement in the cached memory area 
  place <startup_section>        CACHED_RAM
  place <shutdown_section>       CACHED_RAM
  place def_data                 CACHED_RAM
  place def_bss                  CACHED_RAM


  ## Workaround for the lack of CACHE'd RAM with XTVFS included with NDS 4.11 release

  place <myskyepg_nondebug_const> NON_CACHED_RAM
  place <popup_nondebug_const>    NON_CACHED_RAM
  place <myskyepg_debug_const>    NON_CACHED_RAM
  place <popup_debug_const>       NON_CACHED_RAM


  ## Initailse the stack 
  stack CACHED_RAM  (16*K)
  ## Heap takes up the rest of cached memory 
  heap  CACHED_RAM  

  ##
  ## Driver memory segment placements
  ## Associate a label with a memory segment here then in the code you can do, for example,
  ## #pragma ST_section(functiontoplace, "hdosd_RectangleDraw")
  ##
  place os20_th_code             DRIVER_INTERNAL
  place os20_th_data             DRIVER_INTERNAL
  place os20_root_tdesc          DRIVER_INTERNAL
  place os20_task_queue          DRIVER_INTERNAL
  place os20_int_complex_text    DRIVER_INTERNAL
  place os20_int_simple_text     DRIVER_INTERNAL
  place os20_int_moderate_text   DRIVER_INTERNAL

  ## OpenTV KRAPI internal placements
  place memprot_code             DRIVER_INTERNAL
  place is_memprot_code          DRIVER_INTERNAL
  place memprot_segments_data    DRIVER_INTERNAL
  place protsegments_data        DRIVER_INTERNAL
  place o_memset_code            DRIVER_INTERNAL
  place hdosd_PixLineWrite       DRIVER_INTERNAL
  place hdosd_RectangleDraw	   DRIVER_INTERNAL
  place hdosd_RegionGetParams    DRIVER_INTERNAL
  place hrllmem_ttasktests_data  DRIVER_INTERNAL
  place hrllmem_ttasktests_code  DRIVER_INTERNAL
  place hdosd_RectangleAlign     DRIVER_INTERNAL


  ## Place the trap handler in the internal area 
  PlaceDebugTrapHandler          DRIVER_INTERNAL

  ## For reset code - When reset applied, board must NOT be accessing external RAM
  place WaitForResetCode         DRIVER_INTERNAL
  place IntEnablesState          DRIVER_INTERNAL

  ## OpenTV segment placements
  place direct_mem               CACHED_RAM
  place far_mem                  CACHED_RAM

  ## placements for functions that'll cause the system go west if we're running from flash
  place norflash_code            NON_CACHED_RAM
  place teletext_buffers         NON_CACHED_RAM
  
   ## the FPGA programmer
  place <tantofpgainit_text>     CACHED_RAM
##  place <tantofpgainit_const>     CACHED_RAM
  place <tantofpgainit_data>     CACHED_RAM
##  place <tantofpgainit_bss>     CACHED_RAM

   ## the FPGA image and image size variable
  place <tanto_fpga_code_text>  CACHED_RAM
  place <tanto_fpga_code_const>  CACHED_RAM
##  place <tanto_fpga_code_data>  CACHED_RAM
##  place <tanto_fpga_code_bss>  CACHED_RAM

  place <bltnfont_const>		 CACHED_RAM

##  place watchdog_TimerCallback  DRIVER_INTERNAL

  ## Define symbols for the heap, internal and non cached data areas
  ## that can be picked up by the code at run time

  define heap_start "(addressof CACHED_HEAP)"
  define system_heap_size  "(sizeof CACHED_HEAP)"

  define internal_start "(addressof DRIVER_INTERNAL) + (sizeused DRIVER_INTERNAL)"
  define internal_size  "(sizeof DRIVER_INTERNAL)    - (sizeused DRIVER_INTERNAL) - 4"

  define ncache_start "(addressof  NON_CACHED_RAM) + (sizeused NON_CACHED_RAM)"
  define ncache_size  "(sizeof NON_CACHED_RAM) - (sizeused NON_CACHED_RAM)"

  define cfg_font_size "sizeof -q <bltnfont_const>"

}
## end place_cmd_main_general ##

###################################################################
## place_cmd_loader_general - general placements for the loader	###
proc place_cmd_loader_general {
    
  ## create some symbols whose values contain the start addresses and sizes of
  ## EMI0 SDRAMs. 

  cfg_emi0_start = (addressof -q EMI0_SDRAM)
  cfg_emi0_size  = (sizeof -q EMI0_SDRAM)

  ## The whole of the internal memory is available to the drivers
  ## for general data placement, except for the boot cookie area
  driver_internal_start  = (addressof -q INTERNAL)
  driver_internal_size   = (sizeof -q INTERNAL)-256
  cookie_start				 = (addressof -q INTERNAL)+driver_internal_size
  cookie_size				 = 256

  ## Bottom 8M of EMI SDRAM is non cacheable
  non_cached_start = cfg_emi0_start
  non_cached_size  = ( 8*M ) 

  ## Next 1M is for the cacheable heap	- will be used by OS_DymanicMalloc
  cached_heap_start = non_cached_start + non_cached_size 
  cached_heap_size  = ( 1*M )

  ## Define the rest of SMI as the cacheable data area
  cached_size   = cfg_emi0_size - non_cached_size - cached_heap_size
  cached_start  = cfg_emi0_start + non_cached_size + cached_heap_size

  ## Define memory segments 
  memory  NON_CACHED_RAM     (non_cached_start)      (non_cached_size)        RAM
  memory  CACHED_HEAP        (cached_heap_start)     (cached_heap_size)       RAM
  memory  CACHED_RAM         (cached_start)          (cached_size )           RAM
  memory  DRIVER_INTERNAL    (driver_internal_start) (driver_internal_size)   RAM
  memory  COOKIE_MEMORY      (cookie_start)          (cookie_size)            RAM

  ## Default code and data placement in the cached memory area 
  place <startup_section>  CACHED_RAM
  place <shutdown_section> CACHED_RAM
  place def_data           CACHED_RAM
  place def_bss            CACHED_RAM

  ## Place the trap handler in the non cached area
  PlaceDebugTrapHandler     NON_CACHED_RAM

  ## Initailse the stack 
  stack CACHED_RAM  (16*K)
  ## Heap takes up the rest of cached memory 
  heap  CACHED_RAM  

  ##
  ## Driver memory segment placements
  ## Associate a label with a memory segment here then in the code you can do, for example,
  ## #pragma ST_section(functiontoplace, "hdosd_RectangleDraw")
  ##
  place OTV_cookie_mem			 	COOKIE_MEMORY -noinit  
  place IntEnablesState          COOKIE_MEMORY    
  place WaitForResetCode         DRIVER_INTERNAL
  place os20_th_code             DRIVER_INTERNAL
  place os20_th_data             DRIVER_INTERNAL
  place os20_root_tdesc          DRIVER_INTERNAL
  place os20_task_queue          DRIVER_INTERNAL
  place os20_int_complex_text    DRIVER_INTERNAL
  place os20_int_simple_text     DRIVER_INTERNAL
  place os20_int_moderate_text   DRIVER_INTERNAL

  ## OSD component placements
  place hdosd_PixLineWrite       DRIVER_INTERNAL
  place hdosd_RectangleDraw	     DRIVER_INTERNAL
  place hdosd_RegionGetParams    DRIVER_INTERNAL

  ## placements for functions that'll cause the system go west if we're running from flash
  place norflash_code            NON_CACHED_RAM
  place teletext_buffers         NON_CACHED_RAM

  ## the FPGA programmer
  place <tantofpgainit_text>     CACHED_RAM

  ## the FPGA image and image size variable
  place <tanto_fpga_code_text>   CACHED_RAM
  place <tanto_fpga_code_const>  CACHED_RAM

  ## Define symbols for the heap, internal and non cached data areas
  ## that can be picked up by the code at run time

  define heap_start "(addressof CACHED_HEAP)"
  define system_heap_size  "(sizeof CACHED_HEAP)"

  define internal_start "(addressof DRIVER_INTERNAL) + (sizeused DRIVER_INTERNAL)"
  define internal_size  "(sizeof DRIVER_INTERNAL)    - (sizeused DRIVER_INTERNAL) - 4"

  define ncache_start "(addressof  NON_CACHED_RAM) + (sizeused NON_CACHED_RAM)"
  define ncache_size  "(sizeof NON_CACHED_RAM) - (sizeused NON_CACHED_RAM)"

  define cfg_font_size "sizeof -q <bltnfont_const>"

}
## end place_cmd_loader_general ##

######################
## place_cmd_lku ##
proc place_cmd_lku {
    
  ## perform generic placements first 
  place_cmd_main_general

  ## Place code in non cached memory - It will not fit in the cached area 
  ## The Instruction cache is still active in this area	
  place def_code                 NON_CACHED_RAM
  place def_const                NON_CACHED_RAM

  ## ******* RAM build requires Boot data placing *******
  bootdata                 CACHED_RAM

}
## end place_cmd_lku ##

####################
## place_cmd_ldrlku

proc place_cmd_ldrlku {
    
  ## perform generic placements first 
  place_cmd_loader_general

  place def_code           CACHED_RAM
  place def_const          CACHED_RAM
  place serialisation_data CACHED_RAM