product.cfg

来自「flash programming STI 5.5.1.4 DCU3」· CFG 代码 · 共 715 行 · 第 1/2 页

  ## ******* RAM build requires Boot data placing *******
  bootdata                 CACHED_RAM

} ## End place_cmd_ldrlku ##

########################
## place_cmd_main_rom ##

proc place_cmd_main_rom {
   
  ## Extra Placements for rom builds (non included in general procedure)

  ## perform generic placements first 
  place_cmd_main_general

  ## Place code in non cached memory - It will not fit in the cached area 
  ## The Instruction cache is still active in this area	
  place def_code                 NON_CACHED_RAM
  place def_const                CACHED_RAM

  ## ******* ROM build requires Boot instruction pointer *******
  ##  memory  BOOT          (CONFIG_ADDR)       (CONFIG_SIZE)         ROM          
  ## write MAIN CODE = -x ( FLASH_NORMAL_ADDR ) size = -d ( FLASH_BANK_SIZE-CONFIG_SIZE ) 
  ## Removed RT020902 write MAIN BOOT ADDR = -x ( (CONFIG_ADDR)-2 ) 
  ## Removed RT020902 write MAIN BOOT ADDRESS = -x ((CONFIG_ADDR)-2) 
  ## Removed RT020902 bootiptr ((CONFIG_ADDR)-2 ) 

  ## RT020902 boot address is now supplied as its own variable
  write MAIN BOOT ADDRESS = -x (BOOT_ADDRESS) 
  bootiptr (BOOT_ADDRESS) 
}
## place_cmd_main_rom ##

########################
## place_cmd_main_rom_debug ##

proc place_cmd_main_rom_debug {
   
  ## Extra Placements for rom builds (non included in general procedure)

  ## perform generic placements first 
  place_cmd_main_general

  ## Place code in non cached memory - It will not fit in the cached area 
  ## The Instruction cache is still active in this area	
  place def_code                 NON_CACHED_RAM
  place def_const                NON_CACHED_RAM

  ## ******* ROM build requires Boot instruction pointer *******
  ##  memory  BOOT          (CONFIG_ADDR)       (CONFIG_SIZE)         ROM          
  ## write MAIN CODE = -x ( FLASH_NORMAL_ADDR ) size = -d ( FLASH_BANK_SIZE-CONFIG_SIZE ) 
  ## Removed RT020902 write MAIN BOOT ADDR = -x ( (CONFIG_ADDR)-2 ) 
  ## Removed RT020902 write MAIN BOOT ADDRESS = -x ((CONFIG_ADDR)-2) 
  ## Removed RT020902 bootiptr ((CONFIG_ADDR)-2 ) 

  ## RT020902 boot address is now supplied as its own variable
  write MAIN BOOT ADDRESS = -x (BOOT_ADDRESS) 
  bootiptr (BOOT_ADDRESS) 
}
## place_cmd_main_rom_debug ##

#######################################################################################

proc place_flash_programmer_lku {
    
## Extra Placements for a flash programmer build

  ## perform generic placements first 
  place_cmd_main_general

  place def_code           CACHED_RAM
  place def_const          CACHED_RAM

  ## ******* RAM build requires Boot data placing *******
  bootdata                 CACHED_RAM
}
## place_flash_programmer_lku ##

#################################################
## place_cmd_flash_rom -  For loader flash builds

proc place_cmd_flash_rom {
    
  ## Extra Placements for rom builds (non included in general procedure)

  ## perform generic placements first 
  place_cmd_loader_general

  ## Explicitly place the code and const segments in FLASH
  place def_code           FLASH
  place def_const          FLASH
  ## Removed RT050902 place serialisation_data SERIALISATION
  
} ## place_cmd_flash_rom ##

###########################################################################################################
########## LINK COMMAND PROCEDURES ########################################################################
###########################################################################################################

## Memory configuration for DRAM builds
proc c2ramdebug {
  Board_System_Clock_Configs
  ## RT150702 set up a 3k config area
  ## RT180902 0 means "don't configure for basic loader"
  Board_MemoryMap(3, 0)
  ir_regs
  hddi_regs
  place_cmd_lku
}

## Memory config for loader DRAM builds
proc c2ldrramdebug {
  Board_System_Clock_Configs
  ## Defines in Loader_MemDefs required by flash component 
  Board_MemoryMap_Loader(256, 3, "bank0")
  place_cmd_ldrlku
}

## Memory configuration for integrated loader + drivers + app flash builds
proc c2flashmain {
  Board_System_Clock_Configs

  ## Board_MemoryMap_WithLoader  this will need sorting 
  ## RT150702 set up a 3k config area
  ## Removed RT020902 Board_MemoryMap(3) replaced with 256k config area
  ## RT180902 1 means "configure for basic loader" since this is a flash image build
  Board_MemoryMap(256, 1)
write "*************************************************************************"
write "NOTE: FLASH IMAGE IS DESTINED FOR BANK0  "
write "      OR FLASH1 WITH AN UPGRADER/LOADER IN FLASH0 (BUT RUNS AS FLASH0)!!!"
write "*************************************************************************"
write CONFIG_ADDR = -x (CONFIG_ADDR)

  place_cmd_main_rom
}

###################################################
## c2loaderflash - For non debug loader image build 
proc c2loaderflash {
  Board_System_Clock_Configs
  Board_MemoryMap_Loader(256, 3, "bank0")
  place_cmd_flash_rom
}

##########################################################
## c2loaderflashdebug - For loader binary build with debug
proc c2loaderflashdebug {
  Board_System_Clock_Configs
  Board_MemoryMap_Loader(512, 8, "bank0")
  place_cmd_flash_rom
}

###################################################################################
## c2dummyflash - For loader flash testharn build, BUT placed in main area of flash 
proc c2dummyflash{
  Board_System_Clock_Configs
  Board_MemoryMap_Dummy
  place_cmd_flash_rom
}

## Memory configuration for standalone flash drive builds
proc c2flashmaindebug {
  Board_System_Clock_Configs
  ## RT150702 set up a 8k config area for the flash debug build
  ## TJB put back to 3K since flash debug build should not require romboot debug.
  ## RT180902 0 means "don't configure for basic loader"
  Board_MemoryMap(3, 0)
write "*************************************************************************"
write "NOTE: FLASH IMAGE IS DESTINED FOR BANK0"
write "      OR FLASH1 WITH AN UPGRADER/LOADER IN FLASH0 (BUT RUNS AS FLASH0)!!!"
write "*************************************************************************"
  write CONFIG_ADDR = -x (CONFIG_ADDR)
  place_cmd_main_rom_debug
}

## Memory configuration for hostboot builds
proc c2hostboot {
  Board_System_Host_Boot_Clock_Configs
  Board_MemoryMap_boot
  Board_For_Boot
  place_cmd_hostboot
}

## Memory configuration for hostboot builds
proc c2romboot {
  Board_System_Host_Boot_Clock_Configs
  Board_MemoryMap_boot
  Board_For_Boot
  place_cmd_romboot
}

###############################################
## c2rombootbin - For loader debug binary build, 
proc c2rombootbin {
  Board_System_Host_Boot_Clock_Configs
  Board_MemoryMap_boot_bin
  Board_For_Boot
  place_cmd_romboot
}

## Memory configuration for hostboot builds
proc c2stripedromboot {
  Board_System_Host_Boot_Clock_Configs
  Board_MemoryMap_boot
  Board_MemoryMap_stripedbootEXT   ## extension for PLACING FPGA code into
  write NOTE: FLASH IMAGE IS __ONLY EVER__ DESTINED FOR BANK0 !!!
  Board_For_Boot
  place_cmd_striped_romboot
}

## Memory configuration for field trial debug boot loader builds

proc c2debugrombootloader {
  Board_System_Clock_Configs
  Board_MemoryMap_FieldTrialFlashloader

  Board_For_FieldTrialFlash   ## extension for PLACING FPGA code into
  write NOTE: FLASH IMAGE IS __ONLY EVER__ DESTINED FOR BANK0 !!!
  write CONFIG_ADDR = -x (CONFIG_ADDR)
  place_cmd_main_rom

  place           memory_critical_reboot             DRIVER_INTERNAL 

  define debugldr_boot_cookie ((addressof -q DRIVER_INTERNAL)+(sizeof -q DRIVER_INTERNAL)-4)
}

## Memory configuration for Test Harness and flash programmer build
proc TestharnPlace {
  Board_System_Clock_Configs

  Board_MemoryMapTestharness
  place_flash_programmer_lku
}

###########################################################################################################
############## RUN TARGETS ################################################################################
###########################################################################################################


proc htiramdebug {
  StallCPU
  c2ramdebug
}

proc htiramtestharn {
  StallCPU
  TestharnPlace
write FLASH addr is -x (FLASH_NORMAL_ADDR)
write FLASH size is -d (FLASH_NORMAL_SIZE)

}

proc htiromdebugmain {
  StallCPU
  c2flashmaindebug
  program -new ../build/drivers.dbg

  events -all -remove
  break -h main
  runtime c2os20

  go
}

proc htiromconnectmain {
  c2flashmaindebug
  program -new ../build/drivers.dbg
  runtime c2ucos
}

proc htihostboot {
 reset -full 
 c2hostboot
 ST20C2MemoryInit
}

proc rombootdebug {
  reset -full
  c2romboot
  ST20C2MemoryInit
  program -new A191romboot.dbg

  events -all -remove
  break -h main
	
  go
}

proc Stripedrombootdebug {
  reset -full
  c2stripedromboot
##  removed as there's not declaration of this in the new DCU R1_9_5 toolset
##  reset_dcu_compare
  ST20C2MemoryInit
  program -new A191stripedromboot.dbg

  events -all -remove
  break -h main
	
  go
}

proc romFTflashloaderdebug {
  StallCPU
  ST20C2MemoryInit
  c2debugrombootloader
##  removed as there's not declaration of this in the new DCU R1_9_5 toolset
##  reset_dcu_compare
  program -new a191ftflashldr.dbg

  events -all -remove
  break -h main
	
  go
}


## JEI DRAM run procedure
proc jeiramdebug {
	htiramdebug
}

## JPI flash run procedure
proc jpiromdebugmain {
	htiromdebugmain
}

## JPI DRAM run procedure
proc jpiramdebug {
	htiramdebug
}

## JEI hostboot run procedure
proc jeihostboot {
	htihostboot
}

## JPI hostboot run procedure
proc jpihostboot {
	htihostboot
}

###########################################################################################################
############## RUN TARGET CREATION ########################################################################
###########################################################################################################


Targets_Create("htiramtestharn",      "htiramtestharn"     )
Targets_Create("htiramdebug",         "htiramdebug"        )
Targets_Create("htiromdebugmain",     "htiromdebugmain"    )
Targets_Create("htihostboot",         "htihostboot"        )
Targets_Create("htiromconnectmain",   "htiromconnectmain"  ) 
Targets_Create("rombootdebug",        "rombootdebug"       )
Targets_Create("Stripedrombootdebug", "Stripedrombootdebug")
Targets_Create("romFTflashloaderdebug", "romFTflashloaderdebug")