prev_cmp_alltest.qmsg

来自「EPM1270下的 LED闪烁程序」· QMSG 代码 · 共 7 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus II " "Info: Running Quartus II Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 15 11:27:11 2009 " "Info: Processing started: Thu Jan 15 11:27:11 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AllTest -c AllTest --generate_symbol=LCD1602.v " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AllTest -c AllTest --generate_symbol=LCD1602.v" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "LCD1602.v(112) " "Warning (10268): Verilog HDL information at LCD1602.v(112): Always Construct contains both blocking and non-blocking assignments" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 112 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"endmodule\";  expecting an identifier (\"endmodule\" is a reserved keyword ), or \"module\", or \"macromodule\", or \"function\", or \"parameter\", or \"primitive\", or \"real\", or \"realtime\", or \"reg\", or \"specparam\", or \"supply0\", or \"task\", or \"time\", or \"tri\", or \"tri0\", or \"tri1\", or \"triand\", or \"trior\", or \"trireg\", or \"wand\", or \"wire\", or \"integer\", or \"localparam\", or \"(*\", or \"config\", or \"include\", or \"library\" LCD1602.v(224) " "Error (10170): Verilog HDL syntax error at LCD1602.v(224) near text \"endmodule\";  expecting an identifier (\"endmodule\" is a reserved keyword ), or \"module\", or \"macromodule\", or \"function\", or \"parameter\", or \"primitive\", or \"real\", or \"realtime\", or \"reg\", or \"specparam\", or \"supply0\", or \"task\", or \"time\", or \"tri\", or \"tri0\", or \"tri1\", or \"triand\", or \"trior\", or \"trireg\", or \"wand\", or \"wire\", or \"integer\", or \"localparam\", or \"(*\", or \"config\", or \"include\", or \"library\"" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 224 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Create Symbol File 1  0 s Quartus II " "Error: Quartus II Create Symbol File was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "133 " "Info: Allocated 133 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jan 15 11:27:11 2009 " "Error: Processing ended: Thu Jan 15 11:27:11 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}