prev_cmp_alltest.fit.qmsg

EPM1270下的 LED闪烁程序

{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" {  } {  } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.240 ns register register " "Info: Estimated most critical path is register to register delay of 8.240 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FLASH_LED:inst\|cntr\[6\] 1 REG LAB_X2_Y7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y7; Fanout = 4; REG Node = 'FLASH_LED:inst\|cntr\[6\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_LED:inst|cntr[6] } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.010 ns) + CELL(0.978 ns) 2.988 ns FLASH_LED:inst\|Add0~528 2 COMB LAB_X4_Y7 2 " "Info: 2: + IC(2.010 ns) + CELL(0.978 ns) = 2.988 ns; Loc. = LAB_X4_Y7; Fanout = 2; COMB Node = 'FLASH_LED:inst\|Add0~528'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.988 ns" { FLASH_LED:inst|cntr[6] FLASH_LED:inst|Add0~528 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 3.111 ns FLASH_LED:inst\|Add0~530 3 COMB LAB_X4_Y7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.111 ns; Loc. = LAB_X4_Y7; Fanout = 2; COMB Node = 'FLASH_LED:inst\|Add0~530'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { FLASH_LED:inst|Add0~528 FLASH_LED:inst|Add0~530 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 3.234 ns FLASH_LED:inst\|Add0~526 4 COMB LAB_X4_Y7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.234 ns; Loc. = LAB_X4_Y7; Fanout = 2; COMB Node = 'FLASH_LED:inst\|Add0~526'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { FLASH_LED:inst|Add0~530 FLASH_LED:inst|Add0~526 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 3.357 ns FLASH_LED:inst\|Add0~520 5 COMB LAB_X4_Y7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 3.357 ns; Loc. = LAB_X4_Y7; Fanout = 2; COMB Node = 'FLASH_LED:inst\|Add0~520'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { FLASH_LED:inst|Add0~526 FLASH_LED:inst|Add0~520 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 3.756 ns FLASH_LED:inst\|Add0~524 6 COMB LAB_X4_Y7 6 " "Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 3.756 ns; Loc. = LAB_X4_Y7; Fanout = 6; COMB Node = 'FLASH_LED:inst\|Add0~524'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.399 ns" { FLASH_LED:inst|Add0~520 FLASH_LED:inst|Add0~524 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.246 ns) 4.002 ns FLASH_LED:inst\|Add0~514 7 COMB LAB_X4_Y7 6 " "Info: 7: + IC(0.000 ns) + CELL(0.246 ns) = 4.002 ns; Loc. = LAB_X4_Y7; Fanout = 6; COMB Node = 'FLASH_LED:inst\|Add0~514'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.246 ns" { FLASH_LED:inst|Add0~524 FLASH_LED:inst|Add0~514 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.246 ns) 4.248 ns FLASH_LED:inst\|Add0~506 8 COMB LAB_X5_Y7 6 " "Info: 8: + IC(0.000 ns) + CELL(0.246 ns) = 4.248 ns; Loc. = LAB_X5_Y7; Fanout = 6; COMB Node = 'FLASH_LED:inst\|Add0~506'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.246 ns" { FLASH_LED:inst|Add0~514 FLASH_LED:inst|Add0~506 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.246 ns) 4.494 ns FLASH_LED:inst\|Add0~492 9 COMB LAB_X5_Y7 6 " "Info: 9: + IC(0.000 ns) + CELL(0.246 ns) = 4.494 ns; Loc. = LAB_X5_Y7; Fanout = 6; COMB Node = 'FLASH_LED:inst\|Add0~492'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.246 ns" { FLASH_LED:inst|Add0~506 FLASH_LED:inst|Add0~492 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 5.728 ns FLASH_LED:inst\|Add0~489 10 COMB LAB_X6_Y7 1 " "Info: 10: + IC(0.000 ns) + CELL(1.234 ns) = 5.728 ns; Loc. = LAB_X6_Y7; Fanout = 1; COMB Node = 'FLASH_LED:inst\|Add0~489'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { FLASH_LED:inst|Add0~492 FLASH_LED:inst|Add0~489 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.329 ns) + CELL(1.183 ns) 8.240 ns FLASH_LED:inst\|cntr\[26\] 11 REG LAB_X8_Y7 4 " "Info: 11: + IC(1.329 ns) + CELL(1.183 ns) = 8.240 ns; Loc. = LAB_X8_Y7; Fanout = 4; REG Node = 'FLASH_LED:inst\|cntr\[26\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { FLASH_LED:inst|Add0~489 FLASH_LED:inst|cntr[26] } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.901 ns ( 59.48 % ) " "Info: Total cell delay = 4.901 ns ( 59.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.339 ns ( 40.52 % ) " "Info: Total interconnect delay = 3.339 ns ( 40.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.240 ns" { FLASH_LED:inst|cntr[6] FLASH_LED:inst|Add0~528 FLASH_LED:inst|Add0~530 FLASH_LED:inst|Add0~526 FLASH_LED:inst|Add0~520 FLASH_LED:inst|Add0~524 FLASH_LED:inst|Add0~514 FLASH_LED:inst|Add0~506 FLASH_LED:inst|Add0~492 FLASH_LED:inst|Add0~489 FLASH_LED:inst|cntr[26] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X0_Y0 X8_Y11 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Nailson/MCU/CPLD/AllTest/AllTest.fit.smsg " "Info: Generated suppressed messages file D:/Nailson/MCU/CPLD/AllTest/AllTest.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "167 " "Info: Allocated 167 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 14 17:50:37 2009 " "Info: Processing ended: Wed Jan 14 17:50:37 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}