alltest.map.qmsg

EPM1270下的 LED闪烁程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 15 13:19:08 2009 " "Info: Processing started: Thu Jan 15 13:19:08 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AllTest -c AllTest " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AllTest -c AllTest" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AllTest.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file AllTest.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AllTest " "Info: Found entity 1: AllTest" {  } { { "AllTest.bdf" "" { Schematic "D:/Nailson/MCU/CPLD/AllTest/AllTest.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "FLASH_LED.v(25) " "Warning (10268): Verilog HDL information at FLASH_LED.v(25): Always Construct contains both blocking and non-blocking assignments" {  } { { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 25 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FLASH_LED.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FLASH_LED.v" { { "Info" "ISGN_ENTITY_NAME" "1 FLASH_LED " "Info: Found entity 1: FLASH_LED" {  } { { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "LCD1602.v(113) " "Warning (10268): Verilog HDL information at LCD1602.v(113): Always Construct contains both blocking and non-blocking assignments" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 113 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD1602.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD1602.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD1602 " "Info: Found entity 1: LCD1602" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "AllTest " "Info: Elaborating entity \"AllTest\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FLASH_LED FLASH_LED:inst " "Info: Elaborating entity \"FLASH_LED\" for hierarchy \"FLASH_LED:inst\"" {  } { { "AllTest.bdf" "inst" { Schematic "D:/Nailson/MCU/CPLD/AllTest/AllTest.bdf" { { -256 1736 1832 -160 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "78 " "Info: Implemented 78 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "75 " "Info: Implemented 75 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Nailson/MCU/CPLD/AllTest/AllTest.map.smsg " "Info: Generated suppressed messages file D:/Nailson/MCU/CPLD/AllTest/AllTest.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "142 " "Info: Allocated 142 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 15 13:19:11 2009 " "Info: Processing ended: Thu Jan 15 13:19:11 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}