alltest.tan.qmsg

EPM1270下的 LED闪烁程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "AllTest.bdf" "" { Schematic "D:/Nailson/MCU/CPLD/AllTest/AllTest.bdf" { { -232 1528 1696 -216 "clk" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register FLASH_LED:inst\|cntr\[12\] register FLASH_LED:inst\|cntr\[16\] 108.92 MHz 9.181 ns Internal " "Info: Clock \"clk\" has Internal fmax of 108.92 MHz between source register \"FLASH_LED:inst\|cntr\[12\]\" and destination register \"FLASH_LED:inst\|cntr\[16\]\" (period= 9.181 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.472 ns + Longest register register " "Info: + Longest register to register delay is 8.472 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FLASH_LED:inst\|cntr\[12\] 1 REG LC_X2_Y7_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y7_N7; Fanout = 4; REG Node = 'FLASH_LED:inst\|cntr\[12\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_LED:inst|cntr[12] } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.443 ns) + CELL(0.747 ns) 3.190 ns FLASH_LED:inst\|Add0~522 2 COMB LC_X4_Y7_N6 2 " "Info: 2: + IC(2.443 ns) + CELL(0.747 ns) = 3.190 ns; Loc. = LC_X4_Y7_N6; Fanout = 2; COMB Node = 'FLASH_LED:inst\|Add0~522'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { FLASH_LED:inst|cntr[12] FLASH_LED:inst|Add0~522 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 3.313 ns FLASH_LED:inst\|Add0~516 3 COMB LC_X4_Y7_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.313 ns; Loc. = LC_X4_Y7_N7; Fanout = 2; COMB Node = 'FLASH_LED:inst\|Add0~516'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { FLASH_LED:inst|Add0~522 FLASH_LED:inst|Add0~516 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 3.436 ns FLASH_LED:inst\|Add0~510 4 COMB LC_X4_Y7_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.436 ns; Loc. = LC_X4_Y7_N8; Fanout = 2; COMB Node = 'FLASH_LED:inst\|Add0~510'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { FLASH_LED:inst|Add0~516 FLASH_LED:inst|Add0~510 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 3.835 ns FLASH_LED:inst\|Add0~514 5 COMB LC_X4_Y7_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.399 ns) = 3.835 ns; Loc. = LC_X4_Y7_N9; Fanout = 6; COMB Node = 'FLASH_LED:inst\|Add0~514'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.399 ns" { FLASH_LED:inst|Add0~510 FLASH_LED:inst|Add0~514 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 5.069 ns FLASH_LED:inst\|Add0~511 6 COMB LC_X5_Y7_N0 1 " "Info: 6: + IC(0.000 ns) + CELL(1.234 ns) = 5.069 ns; Loc. = LC_X5_Y7_N0; Fanout = 1; COMB Node = 'FLASH_LED:inst\|Add0~511'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { FLASH_LED:inst|Add0~514 FLASH_LED:inst|Add0~511 } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.123 ns) + CELL(0.280 ns) 8.472 ns FLASH_LED:inst\|cntr\[16\] 7 REG LC_X2_Y7_N5 4 " "Info: 7: + IC(3.123 ns) + CELL(0.280 ns) = 8.472 ns; Loc. = LC_X2_Y7_N5; Fanout = 4; REG Node = 'FLASH_LED:inst\|cntr\[16\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.403 ns" { FLASH_LED:inst|Add0~511 FLASH_LED:inst|cntr[16] } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.906 ns ( 34.30 % ) " "Info: Total cell delay = 2.906 ns ( 34.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.566 ns ( 65.70 % ) " "Info: Total interconnect delay = 5.566 ns ( 65.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.472 ns" { FLASH_LED:inst|cntr[12] FLASH_LED:inst|Add0~522 FLASH_LED:inst|Add0~516 FLASH_LED:inst|Add0~510 FLASH_LED:inst|Add0~514 FLASH_LED:inst|Add0~511 FLASH_LED:inst|cntr[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.472 ns" { FLASH_LED:inst|cntr[12] {} FLASH_LED:inst|Add0~522 {} FLASH_LED:inst|Add0~516 {} FLASH_LED:inst|Add0~510 {} FLASH_LED:inst|Add0~514 {} FLASH_LED:inst|Add0~511 {} FLASH_LED:inst|cntr[16] {} } { 0.000ns 2.443ns 0.000ns 0.000ns 0.000ns 0.000ns 3.123ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.399ns 1.234ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 33 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "AllTest.bdf" "" { Schematic "D:/Nailson/MCU/CPLD/AllTest/AllTest.bdf" { { -232 1528 1696 -216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns FLASH_LED:inst\|cntr\[16\] 2 REG LC_X2_Y7_N5 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X2_Y7_N5; Fanout = 4; REG Node = 'FLASH_LED:inst\|cntr\[16\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk FLASH_LED:inst|cntr[16] } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk FLASH_LED:inst|cntr[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} FLASH_LED:inst|cntr[16] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 33 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "AllTest.bdf" "" { Schematic "D:/Nailson/MCU/CPLD/AllTest/AllTest.bdf" { { -232 1528 1696 -216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns FLASH_LED:inst\|cntr\[12\] 2 REG LC_X2_Y7_N7 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X2_Y7_N7; Fanout = 4; REG Node = 'FLASH_LED:inst\|cntr\[12\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk FLASH_LED:inst|cntr[12] } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk FLASH_LED:inst|cntr[12] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} FLASH_LED:inst|cntr[12] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk FLASH_LED:inst|cntr[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} FLASH_LED:inst|cntr[16] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk FLASH_LED:inst|cntr[12] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} FLASH_LED:inst|cntr[12] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 39 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 39 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.472 ns" { FLASH_LED:inst|cntr[12] FLASH_LED:inst|Add0~522 FLASH_LED:inst|Add0~516 FLASH_LED:inst|Add0~510 FLASH_LED:inst|Add0~514 FLASH_LED:inst|Add0~511 FLASH_LED:inst|cntr[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.472 ns" { FLASH_LED:inst|cntr[12] {} FLASH_LED:inst|Add0~522 {} FLASH_LED:inst|Add0~516 {} FLASH_LED:inst|Add0~510 {} FLASH_LED:inst|Add0~514 {} FLASH_LED:inst|Add0~511 {} FLASH_LED:inst|cntr[16] {} } { 0.000ns 2.443ns 0.000ns 0.000ns 0.000ns 0.000ns 3.123ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.399ns 1.234ns 0.280ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk FLASH_LED:inst|cntr[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} FLASH_LED:inst|cntr[16] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk FLASH_LED:inst|cntr[12] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} FLASH_LED:inst|cntr[12] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk LED1 FLASH_LED:inst\|ctrl_out 8.674 ns register " "Info: tco from clock \"clk\" to destination pin \"LED1\" through register \"FLASH_LED:inst\|ctrl_out\" is 8.674 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 33 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "AllTest.bdf" "" { Schematic "D:/Nailson/MCU/CPLD/AllTest/AllTest.bdf" { { -232 1528 1696 -216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns FLASH_LED:inst\|ctrl_out 2 REG LC_X1_Y7_N2 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X1_Y7_N2; Fanout = 2; REG Node = 'FLASH_LED:inst\|ctrl_out'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk FLASH_LED:inst|ctrl_out } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk FLASH_LED:inst|ctrl_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} FLASH_LED:inst|ctrl_out {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.479 ns + Longest register pin " "Info: + Longest register to pin delay is 4.479 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FLASH_LED:inst\|ctrl_out 1 REG LC_X1_Y7_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N2; Fanout = 2; REG Node = 'FLASH_LED:inst\|ctrl_out'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_LED:inst|ctrl_out } "NODE_NAME" } } { "FLASH_LED.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.157 ns) + CELL(2.322 ns) 4.479 ns LED1 2 PIN PIN_30 0 " "Info: 2: + IC(2.157 ns) + CELL(2.322 ns) = 4.479 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'LED1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.479 ns" { FLASH_LED:inst|ctrl_out LED1 } "NODE_NAME" } } { "AllTest.bdf" "" { Schematic "D:/Nailson/MCU/CPLD/AllTest/AllTest.bdf" { { -232 1848 2024 -216 "LED1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 51.84 % ) " "Info: Total cell delay = 2.322 ns ( 51.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.157 ns ( 48.16 % ) " "Info: Total interconnect delay = 2.157 ns ( 48.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.479 ns" { FLASH_LED:inst|ctrl_out LED1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.479 ns" { FLASH_LED:inst|ctrl_out {} LED1 {} } { 0.000ns 2.157ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk FLASH_LED:inst|ctrl_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} FLASH_LED:inst|ctrl_out {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.479 ns" { FLASH_LED:inst|ctrl_out LED1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.479 ns" { FLASH_LED:inst|ctrl_out {} LED1 {} } { 0.000ns 2.157ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 15 13:19:19 2009 " "Info: Processing ended: Thu Jan 15 13:19:19 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}